179 lines
8.4 KiB
Plaintext
179 lines
8.4 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s
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--- |
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define dso_local arm_aapcs_vfpcc void @non_masked_store(i8* noalias nocapture %res, i8* nocapture readonly %a, i8* nocapture readonly %b, i32 %N) {
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entry:
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%cmp10 = icmp eq i32 %N, 0
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%0 = add i32 %N, 15
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%1 = lshr i32 %0, 4
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%2 = shl nuw i32 %1, 4
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%3 = add i32 %2, -16
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%4 = lshr i32 %3, 4
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%5 = add nuw nsw i32 %4, 1
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br i1 %cmp10, label %for.cond.cleanup, label %vector.ph
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vector.ph: ; preds = %entry
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%start = call i32 @llvm.start.loop.iterations.i32(i32 %5)
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br label %vector.body
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vector.body: ; preds = %vector.body, %vector.ph
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%lsr.iv19 = phi i8* [ %scevgep20, %vector.body ], [ %res, %vector.ph ]
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%lsr.iv16 = phi i8* [ %scevgep17, %vector.body ], [ %b, %vector.ph ]
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%lsr.iv = phi i8* [ %scevgep, %vector.body ], [ %a, %vector.ph ]
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%6 = phi i32 [ %start, %vector.ph ], [ %11, %vector.body ]
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%7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]
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%lsr.iv1921 = bitcast i8* %lsr.iv19 to <16 x i8>*
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%lsr.iv1618 = bitcast i8* %lsr.iv16 to <16 x i8>*
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%lsr.iv15 = bitcast i8* %lsr.iv to <16 x i8>*
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%8 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %7)
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%9 = sub i32 %7, 16
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%wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %lsr.iv15, i32 1, <16 x i1> %8, <16 x i8> undef)
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%wide.masked.load14 = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %lsr.iv1618, i32 1, <16 x i1> %8, <16 x i8> undef)
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%10 = add <16 x i8> %wide.masked.load14, %wide.masked.load
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store <16 x i8> %10, <16 x i8>* %lsr.iv1921
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%scevgep = getelementptr i8, i8* %lsr.iv, i32 16
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%scevgep17 = getelementptr i8, i8* %lsr.iv16, i32 16
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%scevgep20 = getelementptr i8, i8* %lsr.iv19, i32 16
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%11 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1)
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%12 = icmp ne i32 %11, 0
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br i1 %12, label %vector.body, label %for.cond.cleanup
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for.cond.cleanup: ; preds = %vector.body, %entry
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ret void
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}
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declare <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>*, i32 immarg, <16 x i1>, <16 x i8>)
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declare void @llvm.masked.store.v16i8.p0v16i8(<16 x i8>, <16 x i8>*, i32 immarg, <16 x i1>)
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declare i32 @llvm.start.loop.iterations.i32(i32)
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declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
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declare <16 x i1> @llvm.arm.mve.vctp8(i32)
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...
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---
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name: non_masked_store
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers: []
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r1', virtual-reg: '' }
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- { reg: '$r2', virtual-reg: '' }
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- { reg: '$r3', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 8
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack:
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- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: non_masked_store
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; CHECK: bb.0.entry:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
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; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
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; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
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; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
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; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7
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; CHECK: tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: t2IT 0, 8, implicit-def $itstate
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; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
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; CHECK: bb.1.vector.ph:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: liveins: $r0, $r1, $r2, $r3
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; CHECK: renamable $r12 = t2ADDri renamable $r3, 15, 14 /* CC::al */, $noreg, $noreg
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; CHECK: renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: renamable $r12 = t2BICri killed renamable $r12, 15, 14 /* CC::al */, $noreg, $noreg
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; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 16, 14 /* CC::al */, $noreg, $noreg
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; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 35, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $lr = t2DLS killed renamable $lr
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; CHECK: bb.2.vector.body:
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; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
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; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
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; CHECK: renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg
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; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg
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; CHECK: MVE_VPST 4, implicit $vpr
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; CHECK: renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv15, align 1)
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; CHECK: renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv1618, align 1)
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; CHECK: renamable $q0 = MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
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; CHECK: renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, $noreg :: (store 16 into %ir.lsr.iv1921, align 1)
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; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
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; CHECK: bb.3.for.cond.cleanup:
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; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
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bb.0.entry:
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successors: %bb.1(0x80000000)
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liveins: $r0, $r1, $r2, $r3, $lr
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frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp
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frame-setup CFI_INSTRUCTION def_cfa_offset 8
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frame-setup CFI_INSTRUCTION offset $lr, -4
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frame-setup CFI_INSTRUCTION offset $r7, -8
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$r7 = frame-setup tMOVr $sp, 14, $noreg
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frame-setup CFI_INSTRUCTION def_cfa_register $r7
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tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr
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t2IT 0, 8, implicit-def $itstate
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tPOP_RET 0, killed $cpsr, def $r7, def $pc, implicit killed $itstate
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bb.1.vector.ph:
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successors: %bb.2(0x80000000)
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liveins: $r0, $r1, $r2, $r3, $lr
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renamable $r12 = t2ADDri renamable $r3, 15, 14, $noreg, $noreg
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renamable $lr = t2MOVi 1, 14, $noreg, $noreg
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renamable $r12 = t2BICri killed renamable $r12, 15, 14, $noreg, $noreg
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renamable $r12 = t2SUBri killed renamable $r12, 16, 14, $noreg, $noreg
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renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 35, 14, $noreg, $noreg
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$lr = t2DoLoopStart renamable $lr
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bb.2.vector.body:
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successors: %bb.2(0x7c000000), %bb.3(0x04000000)
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liveins: $lr, $r0, $r1, $r2, $r3
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renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg
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renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14, $noreg
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MVE_VPST 4, implicit $vpr
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renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv15, align 1)
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renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1618, align 1)
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renamable $lr = t2LoopDec killed renamable $lr, 1
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renamable $q0 = MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
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renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, $noreg :: (store 16 into %ir.lsr.iv1921, align 1)
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t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
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tB %bb.3, 14, $noreg
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bb.3.for.cond.cleanup:
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tPOP_RET 14, $noreg, def $r7, def $pc
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...
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