154 lines
4.0 KiB
LLVM
154 lines
4.0 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; Test removal of AND operations that don't affect last 6 bits of shift amount
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; operand.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Test that AND is not removed when some lower 6 bits are not set.
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define i32 @f1(i32 %a, i32 %sh) {
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; CHECK-LABEL: f1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nill %r3, 31
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; CHECK-NEXT: sll %r2, 0(%r3)
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; CHECK-NEXT: br %r14
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%and = and i32 %sh, 31
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%shift = shl i32 %a, %and
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ret i32 %shift
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}
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; Test removal of AND mask with only bottom 6 bits set.
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define i32 @f2(i32 %a, i32 %sh) {
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; CHECK-LABEL: f2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sll %r2, 0(%r3)
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; CHECK-NEXT: br %r14
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%and = and i32 %sh, 63
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%shift = shl i32 %a, %and
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ret i32 %shift
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}
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; Test removal of AND mask including but not limited to bottom 6 bits.
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define i32 @f3(i32 %a, i32 %sh) {
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; CHECK-LABEL: f3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sll %r2, 0(%r3)
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; CHECK-NEXT: br %r14
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%and = and i32 %sh, 255
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%shift = shl i32 %a, %and
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ret i32 %shift
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}
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; Test removal of AND mask from SRA.
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define i32 @f4(i32 %a, i32 %sh) {
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; CHECK-LABEL: f4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sra %r2, 0(%r3)
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; CHECK-NEXT: br %r14
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%and = and i32 %sh, 63
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%shift = ashr i32 %a, %and
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ret i32 %shift
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}
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; Test removal of AND mask from SRL.
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define i32 @f5(i32 %a, i32 %sh) {
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; CHECK-LABEL: f5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: srl %r2, 0(%r3)
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; CHECK-NEXT: br %r14
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%and = and i32 %sh, 63
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%shift = lshr i32 %a, %and
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ret i32 %shift
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}
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; Test removal of AND mask from SLLG.
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define i64 @f6(i64 %a, i64 %sh) {
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; CHECK-LABEL: f6:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sllg %r2, %r2, 0(%r3)
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; CHECK-NEXT: br %r14
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%and = and i64 %sh, 63
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%shift = shl i64 %a, %and
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ret i64 %shift
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}
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; Test removal of AND mask from SRAG.
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define i64 @f7(i64 %a, i64 %sh) {
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; CHECK-LABEL: f7:
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; CHECK: # %bb.0:
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; CHECK-NEXT: srag %r2, %r2, 0(%r3)
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; CHECK-NEXT: br %r14
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%and = and i64 %sh, 63
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%shift = ashr i64 %a, %and
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ret i64 %shift
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}
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; Test removal of AND mask from SRLG.
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define i64 @f8(i64 %a, i64 %sh) {
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; CHECK-LABEL: f8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: srlg %r2, %r2, 0(%r3)
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; CHECK-NEXT: br %r14
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%and = and i64 %sh, 63
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%shift = lshr i64 %a, %and
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ret i64 %shift
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}
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; Test that AND with two register operands is not affected.
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define i32 @f9(i32 %a, i32 %b, i32 %sh) {
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; CHECK-LABEL: f9:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nr %r3, %r4
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; CHECK-NEXT: sll %r2, 0(%r3)
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; CHECK-NEXT: br %r14
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%and = and i32 %sh, %b
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%shift = shl i32 %a, %and
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ret i32 %shift
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}
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; Test that AND is not entirely removed if the result is reused.
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define i32 @f10(i32 %a, i32 %sh) {
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; CHECK-LABEL: f10:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sll %r2, 0(%r3)
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; CHECK-NEXT: nilf %r3, 63
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; CHECK-NEXT: ar %r2, %r3
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; CHECK-NEXT: br %r14
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%and = and i32 %sh, 63
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%shift = shl i32 %a, %and
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%reuse = add i32 %and, %shift
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ret i32 %reuse
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}
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; Test that AND is not removed for i128 (which calls __ashlti3)
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define i128 @f11(i128 %a, i32 %sh) {
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; CHECK-LABEL: f11:
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; CHECK: # %bb.0:
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; CHECK-NEXT: stmg %r13, %r15, 104(%r15)
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; CHECK-NEXT: .cfi_offset %r13, -56
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; CHECK-NEXT: .cfi_offset %r14, -48
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; CHECK-NEXT: .cfi_offset %r15, -40
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; CHECK-NEXT: aghi %r15, -192
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; CHECK-NEXT: .cfi_def_cfa_offset 352
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; CHECK-NEXT: lg %r0, 8(%r3)
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; CHECK-NEXT: # kill: def $r4l killed $r4l def $r4d
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; CHECK-NEXT: lgr %r13, %r2
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; CHECK-NEXT: lg %r1, 0(%r3)
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; CHECK-NEXT: stg %r0, 168(%r15)
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; CHECK-NEXT: risbg %r4, %r4, 57, 191, 0
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; CHECK-NEXT: la %r2, 176(%r15)
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; CHECK-NEXT: la %r3, 160(%r15)
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; CHECK-NEXT: stg %r1, 160(%r15)
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; CHECK-NEXT: brasl %r14, __ashlti3@PLT
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; CHECK-NEXT: lg %r0, 184(%r15)
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; CHECK-NEXT: lg %r1, 176(%r15)
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; CHECK-NEXT: stg %r0, 8(%r13)
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; CHECK-NEXT: stg %r1, 0(%r13)
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; CHECK-NEXT: lmg %r13, %r15, 296(%r15)
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; CHECK-NEXT: br %r14
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%and = and i32 %sh, 127
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%ext = zext i32 %and to i128
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%shift = shl i128 %a, %ext
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ret i128 %shift
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}
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