192 lines
6.5 KiB
LLVM
192 lines
6.5 KiB
LLVM
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; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr8 \
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; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr8 -disable-ppc-vsx-swap-removal \
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; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck \
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; RUN: -check-prefix=NOOPTSWAP %s
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; RUN: llc -O3 -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -verify-machineinstrs -ppc-vsr-nums-as-vr < %s | FileCheck \
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; RUN: -check-prefix=CHECK-P9 --implicit-check-not xxswapd %s
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; RUN: llc -O3 -mcpu=pwr9 -disable-ppc-vsx-swap-removal -mattr=-power9-vector \
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; RUN: -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s \
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; RUN: | FileCheck -check-prefix=NOOPTSWAP %s
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; LH: 2016-11-17
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; Updated align attritue from 16 to 8 to keep swap instructions tests.
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; Changes have been made on little-endian to use lvx and stvx
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; instructions instead of lxvd2x/xxswapd and xxswapd/stxvd2x for
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; aligned vectors with elements up to 4 bytes
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; This test was generated from the following source:
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;
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; #define N 4096
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; int ca[N] __attribute__((aligned(16)));
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; int cb[N] __attribute__((aligned(16)));
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; int cc[N] __attribute__((aligned(16)));
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; int cd[N] __attribute__((aligned(16)));
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;
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; void foo ()
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; {
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; int i;
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; for (i = 0; i < N; i++) {
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; ca[i] = (cb[i] + cc[i]) * cd[i];
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; }
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; }
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@cb = common global [4096 x i32] zeroinitializer, align 8
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@cc = common global [4096 x i32] zeroinitializer, align 8
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@cd = common global [4096 x i32] zeroinitializer, align 8
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@ca = common global [4096 x i32] zeroinitializer, align 8
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define void @foo() {
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entry:
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br label %vector.body
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vector.body:
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%index = phi i64 [ 0, %entry ], [ %index.next.3, %vector.body ]
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%0 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cb, i64 0, i64 %index
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%1 = bitcast i32* %0 to <4 x i32>*
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%wide.load = load <4 x i32>, <4 x i32>* %1, align 8
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%2 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cc, i64 0, i64 %index
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%3 = bitcast i32* %2 to <4 x i32>*
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%wide.load13 = load <4 x i32>, <4 x i32>* %3, align 8
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%4 = add nsw <4 x i32> %wide.load13, %wide.load
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%5 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cd, i64 0, i64 %index
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%6 = bitcast i32* %5 to <4 x i32>*
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%wide.load14 = load <4 x i32>, <4 x i32>* %6, align 8
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%7 = mul nsw <4 x i32> %4, %wide.load14
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%8 = getelementptr inbounds [4096 x i32], [4096 x i32]* @ca, i64 0, i64 %index
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%9 = bitcast i32* %8 to <4 x i32>*
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store <4 x i32> %7, <4 x i32>* %9, align 8
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%index.next = add nuw nsw i64 %index, 4
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%10 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cb, i64 0, i64 %index.next
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%11 = bitcast i32* %10 to <4 x i32>*
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%wide.load.1 = load <4 x i32>, <4 x i32>* %11, align 8
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%12 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cc, i64 0, i64 %index.next
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%13 = bitcast i32* %12 to <4 x i32>*
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%wide.load13.1 = load <4 x i32>, <4 x i32>* %13, align 8
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%14 = add nsw <4 x i32> %wide.load13.1, %wide.load.1
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%15 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cd, i64 0, i64 %index.next
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%16 = bitcast i32* %15 to <4 x i32>*
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%wide.load14.1 = load <4 x i32>, <4 x i32>* %16, align 8
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%17 = mul nsw <4 x i32> %14, %wide.load14.1
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%18 = getelementptr inbounds [4096 x i32], [4096 x i32]* @ca, i64 0, i64 %index.next
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%19 = bitcast i32* %18 to <4 x i32>*
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store <4 x i32> %17, <4 x i32>* %19, align 8
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%index.next.1 = add nuw nsw i64 %index.next, 4
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%20 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cb, i64 0, i64 %index.next.1
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%21 = bitcast i32* %20 to <4 x i32>*
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%wide.load.2 = load <4 x i32>, <4 x i32>* %21, align 8
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%22 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cc, i64 0, i64 %index.next.1
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%23 = bitcast i32* %22 to <4 x i32>*
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%wide.load13.2 = load <4 x i32>, <4 x i32>* %23, align 8
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%24 = add nsw <4 x i32> %wide.load13.2, %wide.load.2
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%25 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cd, i64 0, i64 %index.next.1
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%26 = bitcast i32* %25 to <4 x i32>*
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%wide.load14.2 = load <4 x i32>, <4 x i32>* %26, align 8
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%27 = mul nsw <4 x i32> %24, %wide.load14.2
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%28 = getelementptr inbounds [4096 x i32], [4096 x i32]* @ca, i64 0, i64 %index.next.1
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%29 = bitcast i32* %28 to <4 x i32>*
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store <4 x i32> %27, <4 x i32>* %29, align 8
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%index.next.2 = add nuw nsw i64 %index.next.1, 4
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%30 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cb, i64 0, i64 %index.next.2
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%31 = bitcast i32* %30 to <4 x i32>*
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%wide.load.3 = load <4 x i32>, <4 x i32>* %31, align 8
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%32 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cc, i64 0, i64 %index.next.2
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%33 = bitcast i32* %32 to <4 x i32>*
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%wide.load13.3 = load <4 x i32>, <4 x i32>* %33, align 8
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%34 = add nsw <4 x i32> %wide.load13.3, %wide.load.3
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%35 = getelementptr inbounds [4096 x i32], [4096 x i32]* @cd, i64 0, i64 %index.next.2
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%36 = bitcast i32* %35 to <4 x i32>*
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%wide.load14.3 = load <4 x i32>, <4 x i32>* %36, align 8
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%37 = mul nsw <4 x i32> %34, %wide.load14.3
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%38 = getelementptr inbounds [4096 x i32], [4096 x i32]* @ca, i64 0, i64 %index.next.2
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%39 = bitcast i32* %38 to <4 x i32>*
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store <4 x i32> %37, <4 x i32>* %39, align 8
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%index.next.3 = add nuw nsw i64 %index.next.2, 4
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%40 = icmp eq i64 %index.next.3, 4096
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br i1 %40, label %for.end, label %vector.body
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for.end:
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ret void
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}
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; CHECK-LABEL: @foo
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; CHECK-NOT: xxpermdi
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; CHECK-NOT: xxswapd
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; CHECK-P9-NOT: xxpermdi
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; CHECK: lxvd2x
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; CHECK: lxvd2x
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; CHECK-DAG: lxvd2x
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; CHECK-DAG: vadduwm
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; CHECK: vmuluwm
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; CHECK: stxvd2x
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; CHECK: lxvd2x
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; CHECK: lxvd2x
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; CHECK-DAG: lxvd2x
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; CHECK-DAG: vadduwm
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; CHECK: vmuluwm
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; CHECK: stxvd2x
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; CHECK: lxvd2x
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; CHECK: lxvd2x
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; CHECK-DAG: lxvd2x
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; CHECK-DAG: vadduwm
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; CHECK: vmuluwm
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; CHECK: stxvd2x
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; CHECK: lxvd2x
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; CHECK: lxvd2x
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; CHECK-DAG: lxvd2x
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; CHECK-DAG: vadduwm
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; CHECK: vmuluwm
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; CHECK: stxvd2x
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; NOOPTSWAP-LABEL: @foo
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; NOOPTSWAP: lxvd2x
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; NOOPTSWAP-DAG: lxvd2x
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; NOOPTSWAP-DAG: lxvd2x
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; NOOPTSWAP-DAG: xxswapd
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; NOOPTSWAP-DAG: xxswapd
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; NOOPTSWAP-DAG: xxswapd
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; NOOPTSWAP-DAG: vadduwm
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; NOOPTSWAP: vmuluwm
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; NOOPTSWAP: xxswapd
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; NOOPTSWAP-DAG: xxswapd
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; NOOPTSWAP-DAG: xxswapd
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; NOOPTSWAP-DAG: stxvd2x
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; NOOPTSWAP-DAG: stxvd2x
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; NOOPTSWAP: stxvd2x
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; CHECK-P9-LABEL: @foo
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; CHECK-P9-DAG: lxv
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; CHECK-P9-DAG: lxv
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; CHECK-P9-DAG: lxv
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; CHECK-P9-DAG: lxv
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; CHECK-P9-DAG: lxv
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; CHECK-P9-DAG: lxv
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; CHECK-P9-DAG: lxv
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; CHECK-P9-DAG: lxv
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; CHECK-P9-DAG: lxv
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; CHECK-P9-DAG: lxv
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; CHECK-P9-DAG: lxv
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; CHECK-P9-DAG: lxv
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; CHECK-P9-DAG: vadduwm
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; CHECK-P9-DAG: vadduwm
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; CHECK-P9-DAG: vadduwm
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; CHECK-P9-DAG: vadduwm
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; CHECK-P9-DAG: vmuluwm
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; CHECK-P9-DAG: vmuluwm
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; CHECK-P9-DAG: vmuluwm
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; CHECK-P9-DAG: vmuluwm
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; CHECK-P9-DAG: stxv
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; CHECK-P9-DAG: stxv
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; CHECK-P9-DAG: stxv
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; CHECK-P9-DAG: stxv
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