99 lines
2.9 KiB
LLVM
99 lines
2.9 KiB
LLVM
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; RUN: llc -verify-machineinstrs < %s | FileCheck --check-prefix=P8 --check-prefix=CHECK %s
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; RUN: llc -mcpu=pwr9 -verify-machineinstrs < %s | FileCheck --check-prefix=P9 --check-prefix=CHECK %s
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target datalayout = "e-m:e-i64:64-n32:64"
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target triple = "powerpc64le-unknown-linux-gnu"
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; CHECK-LABEL: lshr:
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; CHECK-DAG: subfic [[R0:[0-9]+]], 5, 64
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; CHECK-DAG: addi [[R1:[0-9]+]], 5, -64
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; CHECK-DAG: srd [[R2:[0-9]+]], 3, 5
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; CHECK-DAG: sld [[R3:[0-9]+]], 4, [[R0]]
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; CHECK-DAG: srd [[R4:[0-9]+]], 4, [[R1]]
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; CHECK-DAG: or [[R5:[0-9]+]], [[R2]], [[R3]]
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; CHECK-DAG: or 3, [[R5]], [[R4]]
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; CHECK-DAG: srd 4, 4, 5
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; CHECK: blr
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define i128 @lshr(i128 %x, i128 %y) {
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%r = lshr i128 %x, %y
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ret i128 %r
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}
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; CHECK-LABEL: ashr:
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; CHECK-DAG: subfic [[R0:[0-9]+]], 5, 64
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; CHECK-DAG: addi [[R1:[0-9]+]], 5, -64
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; CHECK-DAG: srd [[R2:[0-9]+]], 3, 5
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; CHECK-DAG: sld [[R3:[0-9]+]], 4, [[R0]]
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; CHECK-DAG: srad [[R4:[0-9]+]], 4, [[R1]]
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; CHECK-DAG: or [[R5:[0-9]+]], [[R2]], [[R3]]
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; CHECK-DAG: cmpwi [[R1]], 1
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; CHECK-DAG: srad 4, 4, 5
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; CHECK-DAG: isellt 3, [[R5]], [[R4]]
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; CHECK: blr
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define i128 @ashr(i128 %x, i128 %y) {
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%r = ashr i128 %x, %y
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ret i128 %r
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}
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; CHECK-LABEL: shl:
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; CHECK-DAG: subfic [[R0:[0-9]+]], 5, 64
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; CHECK-DAG: addi [[R1:[0-9]+]], 5, -64
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; CHECK-DAG: sld [[R2:[0-9]+]], 4, 5
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; CHECK-DAG: srd [[R3:[0-9]+]], 3, [[R0]]
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; CHECK-DAG: sld [[R4:[0-9]+]], 3, [[R1]]
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; CHECK-DAG: or [[R5:[0-9]+]], [[R2]], [[R3]]
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; CHECK-DAG: or 4, [[R5]], [[R4]]
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; CHECK-DAG: sld 3, 3, 5
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; CHECK: blr
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define i128 @shl(i128 %x, i128 %y) {
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%r = shl i128 %x, %y
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ret i128 %r
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}
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; CHECK-LABEL: shl_v1i128:
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; P8-NOT: {{\b}}vslo
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; P8-NOT: {{\b}}vsl
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; P9-DAG: vslo
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; P9-DAG: vspltb
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; P9: vsl
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; P9-NOT: {{\b}}sld
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; P9-NOT: {{\b}}srd
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; CHECK: blr
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define i128 @shl_v1i128(i128 %arg, i128 %amt) local_unnamed_addr #0 {
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entry:
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%0 = insertelement <1 x i128> undef, i128 %arg, i32 0
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%1 = insertelement <1 x i128> undef, i128 %amt, i32 0
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%2 = shl <1 x i128> %0, %1
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%retval = extractelement <1 x i128> %2, i32 0
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ret i128 %retval
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}
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; CHECK-LABEL: lshr_v1i128:
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; P8-NOT: {{\b}}vsro
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; P8-NOT: {{\b}}vsr
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; P9-DAG: vsro
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; P9-DAG: vspltb
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; P9: vsr
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; P9-NOT: {{\b}}srd
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; P9-NOT: {{\b}}sld
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; CHECK: blr
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define i128 @lshr_v1i128(i128 %arg, i128 %amt) local_unnamed_addr #0 {
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entry:
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%0 = insertelement <1 x i128> undef, i128 %arg, i32 0
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%1 = insertelement <1 x i128> undef, i128 %amt, i32 0
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%2 = lshr <1 x i128> %0, %1
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%retval = extractelement <1 x i128> %2, i32 0
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ret i128 %retval
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}
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; Arithmetic shift right is not available as an operation on the vector registers.
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; CHECK-LABEL: ashr_v1i128:
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; CHECK-NOT: {{\b}}vsro
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; CHECK-NOT: {{\b}}vsr
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; CHECK: blr
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define i128 @ashr_v1i128(i128 %arg, i128 %amt) local_unnamed_addr #0 {
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entry:
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%0 = insertelement <1 x i128> undef, i128 %arg, i32 0
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%1 = insertelement <1 x i128> undef, i128 %amt, i32 0
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%2 = ashr <1 x i128> %0, %1
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%retval = extractelement <1 x i128> %2, i32 0
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ret i128 %retval
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}
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