138 lines
3.0 KiB
LLVM
138 lines
3.0 KiB
LLVM
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; RUN: llc -verify-machineinstrs -print-before=peephole-opt -print-after=peephole-opt -mtriple=powerpc64-unknown-linux-gnu -o /dev/null 2>&1 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -print-before=peephole-opt -print-after=peephole-opt -mtriple=powerpc64le-unknown-linux-gnu -o /dev/null 2>&1 < %s | FileCheck %s
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; CHECK-LABEL: fn1
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define signext i32 @fn1(i32 %baz) {
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%1 = mul nsw i32 %baz, 208
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%2 = zext i32 %1 to i64
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%3 = shl i64 %2, 48
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%4 = ashr exact i64 %3, 48
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; CHECK: RLWINM8 killed {{[^,]+}}, 0, 16, 27
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; CHECK: CMPLDI
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; CHECK: BCC
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; CHECK: ANDI8_rec {{[^,]+}}, 65520, implicit-def $cr0
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; CHECK: COPY killed $cr0
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; CHECK: BCC
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%5 = icmp eq i64 %4, 0
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br i1 %5, label %foo, label %bar
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foo:
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ret i32 1
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bar:
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ret i32 0
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}
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; CHECK-LABEL: fn2
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define signext i32 @fn2(i64 %a, i64 %b) {
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; CHECK: OR8_rec {{[^, ]+}}, {{[^, ]+}}, implicit-def $cr0
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; CHECK: [[CREG:[^, ]+]]:crrc = COPY killed $cr
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; CHECK: BCC 12, killed [[CREG]]
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%1 = or i64 %b, %a
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%2 = icmp sgt i64 %1, -1
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br i1 %2, label %foo, label %bar
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foo:
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ret i32 1
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bar:
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ret i32 0
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}
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; CHECK-LABEL: fn3
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define signext i32 @fn3(i32 %a) {
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; CHECK: ANDI_rec killed {{[%0-9]+}}{{[^,]*}}, 10, implicit-def $cr0
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; CHECK: [[CREG:[^, ]+]]:crrc = COPY $cr0
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; CHECK: BCC 76, killed [[CREG]]
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%1 = and i32 %a, 10
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%2 = icmp ne i32 %1, 0
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br i1 %2, label %foo, label %bar
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foo:
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ret i32 1
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bar:
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ret i32 0
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}
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; This test case confirms that a record-form instruction is
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; generated even if the branch has a static branch hint.
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; CHECK-LABEL: fn4
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define i64 @fn4(i64 %a, i64 %b) {
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; CHECK: ADD8_rec
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; CHECK-NOT: CMP
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; CHECK: BCC 71
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entry:
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%add = add nsw i64 %b, %a
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%cmp = icmp eq i64 %add, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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tail call void @exit(i32 signext 0) #3
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unreachable
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if.end:
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ret i64 %add
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}
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declare void @exit(i32 signext)
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; Since %v1 and %v2 are zero-extended 32-bit values, %1 is also zero-extended.
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; In this case, we want to use OR_rec instead of OR + CMPLWI.
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; CHECK-LABEL: fn5
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define zeroext i32 @fn5(i32* %p1, i32* %p2) {
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; CHECK: OR_rec
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; CHECK-NOT: CMP
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; CHECK: BCC
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%v1 = load i32, i32* %p1
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%v2 = load i32, i32* %p2
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%1 = or i32 %v1, %v2
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%2 = icmp eq i32 %1, 0
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br i1 %2, label %foo, label %bar
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foo:
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ret i32 1
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bar:
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ret i32 0
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}
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; This test confirms record-form instructions are emitted for comparison
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; against a non-zero value.
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; CHECK-LABEL: fn6
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define i8* @fn6(i8* readonly %p) {
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; CHECK: LBZU
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; CHECK: EXTSB_rec
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; CHECK-NOT: CMP
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; CHECK: BCC
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; CHECK: LBZU
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; CHECK: EXTSB_rec
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; CHECK-NOT: CMP
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; CHECK: BCC
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entry:
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%incdec.ptr = getelementptr inbounds i8, i8* %p, i64 -1
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%0 = load i8, i8* %incdec.ptr
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%cmp = icmp sgt i8 %0, -1
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br i1 %cmp, label %out, label %if.end
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if.end:
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%incdec.ptr2 = getelementptr inbounds i8, i8* %p, i64 -2
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%1 = load i8, i8* %incdec.ptr2
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%cmp4 = icmp sgt i8 %1, -1
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br i1 %cmp4, label %out, label %cleanup
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out:
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%p.addr.0 = phi i8* [ %incdec.ptr, %entry ], [ %incdec.ptr2, %if.end ]
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br label %cleanup
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cleanup:
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%retval.0 = phi i8* [ %p.addr.0, %out ], [ null, %if.end ]
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ret i8* %retval.0
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}
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