337 lines
13 KiB
LLVM
337 lines
13 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O3 -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \
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; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s
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; RUN: llc -O3 -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \
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; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
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declare <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8>, <16 x i8>)
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declare <512 x i1> @llvm.ppc.mma.xxsetaccz()
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declare <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1>, <256 x i1>, <16 x i8>)
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declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>)
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define void @testPHI1(<16 x i8>* %Dst, <16 x i8>* %Src, i32 signext %Len) {
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; CHECK-LABEL: testPHI1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: cmpwi r5, 3
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; CHECK-NEXT: xxsetaccz acc0
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; CHECK-NEXT: blt cr0, .LBB0_3
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; CHECK-NEXT: # %bb.1: # %for.body.preheader
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; CHECK-NEXT: clrldi r5, r5, 32
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; CHECK-NEXT: lxv vs4, 0(r4)
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; CHECK-NEXT: lxv vs5, 16(r4)
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; CHECK-NEXT: addi r4, r4, 32
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; CHECK-NEXT: addi r5, r5, -2
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; CHECK-NEXT: mtctr r5
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB0_2: # %for.body
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; CHECK-NEXT: #
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; CHECK-NEXT: lxv vs6, 0(r4)
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; CHECK-NEXT: addi r4, r4, 16
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; CHECK-NEXT: xvf64gerpp acc0, vsp4, vs6
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; CHECK-NEXT: bdnz .LBB0_2
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; CHECK-NEXT: .LBB0_3: # %for.cond.cleanup
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; CHECK-NEXT: xxmfacc acc0
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; CHECK-NEXT: stxv vs3, 0(r3)
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; CHECK-NEXT: stxv vs2, 16(r3)
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; CHECK-NEXT: stxv vs1, 32(r3)
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; CHECK-NEXT: stxv vs0, 48(r3)
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: testPHI1:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: cmpwi r5, 3
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; CHECK-BE-NEXT: xxsetaccz acc0
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; CHECK-BE-NEXT: blt cr0, .LBB0_3
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; CHECK-BE-NEXT: # %bb.1: # %for.body.preheader
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; CHECK-BE-NEXT: clrldi r5, r5, 32
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; CHECK-BE-NEXT: lxv vs4, 0(r4)
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; CHECK-BE-NEXT: lxv vs5, 16(r4)
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; CHECK-BE-NEXT: addi r4, r4, 32
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; CHECK-BE-NEXT: addi r5, r5, -2
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; CHECK-BE-NEXT: mtctr r5
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; CHECK-BE-NEXT: .p2align 4
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; CHECK-BE-NEXT: .LBB0_2: # %for.body
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; CHECK-BE-NEXT: #
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; CHECK-BE-NEXT: lxv vs6, 0(r4)
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; CHECK-BE-NEXT: addi r4, r4, 16
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; CHECK-BE-NEXT: xvf64gerpp acc0, vsp4, vs6
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; CHECK-BE-NEXT: bdnz .LBB0_2
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; CHECK-BE-NEXT: .LBB0_3: # %for.cond.cleanup
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; CHECK-BE-NEXT: xxmfacc acc0
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; CHECK-BE-NEXT: stxv vs0, 0(r3)
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; CHECK-BE-NEXT: stxv vs1, 16(r3)
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; CHECK-BE-NEXT: stxv vs2, 32(r3)
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; CHECK-BE-NEXT: stxv vs3, 48(r3)
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; CHECK-BE-NEXT: blr
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entry:
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%0 = load <16 x i8>, <16 x i8>* %Src, align 16
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%arrayidx1 = getelementptr inbounds <16 x i8>, <16 x i8>* %Src, i64 1
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%1 = load <16 x i8>, <16 x i8>* %arrayidx1, align 16
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%2 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %0, <16 x i8> %1)
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%3 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz()
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%cmp11 = icmp sgt i32 %Len, 2
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br i1 %cmp11, label %for.body.preheader, label %for.cond.cleanup
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for.body.preheader:
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%wide.trip.count = zext i32 %Len to i64
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br label %for.body
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for.cond.cleanup:
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%Acc.0.lcssa = phi <512 x i1> [ %3, %entry ], [ %13, %for.body ]
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%4 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %Acc.0.lcssa)
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%5 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %4, 0
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store <16 x i8> %5, <16 x i8>* %Dst, align 16
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%6 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %4, 1
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%7 = getelementptr inbounds <16 x i8>, <16 x i8>* %Dst, i64 1
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store <16 x i8> %6, <16 x i8>* %7, align 16
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%8 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %4, 2
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%9 = getelementptr inbounds <16 x i8>, <16 x i8>* %Dst, i64 2
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store <16 x i8> %8, <16 x i8>* %9, align 16
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%10 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %4, 3
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%11 = getelementptr inbounds <16 x i8>, <16 x i8>* %Dst, i64 3
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store <16 x i8> %10, <16 x i8>* %11, align 16
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ret void
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for.body:
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%indvars.iv = phi i64 [ 2, %for.body.preheader ], [ %indvars.iv.next, %for.body ]
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%Acc.012 = phi <512 x i1> [ %3, %for.body.preheader ], [ %13, %for.body ]
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%arrayidx2 = getelementptr inbounds <16 x i8>, <16 x i8>* %Src, i64 %indvars.iv
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%12 = load <16 x i8>, <16 x i8>* %arrayidx2, align 16
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%13 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %Acc.012, <256 x i1> %2, <16 x i8> %12)
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
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br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
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}
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declare <512 x i1> @llvm.ppc.mma.xvf64ger(<256 x i1>, <16 x i8>)
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define dso_local void @testPHI2(<16 x i8>* %Dst, <16 x i8>* %Src, i32 signext %Len) {
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; CHECK-LABEL: testPHI2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxv vs4, 0(r4)
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; CHECK-NEXT: lxv vs5, 16(r4)
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; CHECK-NEXT: lxv vs6, 32(r4)
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; CHECK-NEXT: cmpwi r5, 4
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; CHECK-NEXT: xvf64ger acc0, vsp4, vs6
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; CHECK-NEXT: blt cr0, .LBB1_3
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; CHECK-NEXT: # %bb.1: # %for.body.preheader
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; CHECK-NEXT: clrldi r5, r5, 32
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; CHECK-NEXT: addi r4, r4, 48
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; CHECK-NEXT: addi r5, r5, -3
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; CHECK-NEXT: mtctr r5
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB1_2: # %for.body
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; CHECK-NEXT: #
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; CHECK-NEXT: lxv vs6, 0(r4)
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; CHECK-NEXT: addi r4, r4, 16
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; CHECK-NEXT: xvf64gerpp acc0, vsp4, vs6
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; CHECK-NEXT: bdnz .LBB1_2
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; CHECK-NEXT: .LBB1_3: # %for.cond.cleanup
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; CHECK-NEXT: xxmfacc acc0
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; CHECK-NEXT: stxv vs3, 0(r3)
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; CHECK-NEXT: stxv vs2, 16(r3)
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; CHECK-NEXT: stxv vs1, 32(r3)
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; CHECK-NEXT: stxv vs0, 48(r3)
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: testPHI2:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: lxv vs4, 0(r4)
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; CHECK-BE-NEXT: lxv vs5, 16(r4)
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; CHECK-BE-NEXT: lxv vs6, 32(r4)
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; CHECK-BE-NEXT: cmpwi r5, 4
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; CHECK-BE-NEXT: xvf64ger acc0, vsp4, vs6
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; CHECK-BE-NEXT: blt cr0, .LBB1_3
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; CHECK-BE-NEXT: # %bb.1: # %for.body.preheader
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; CHECK-BE-NEXT: clrldi r5, r5, 32
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; CHECK-BE-NEXT: addi r4, r4, 48
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; CHECK-BE-NEXT: addi r5, r5, -3
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; CHECK-BE-NEXT: mtctr r5
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; CHECK-BE-NEXT: .p2align 4
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; CHECK-BE-NEXT: .LBB1_2: # %for.body
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; CHECK-BE-NEXT: #
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; CHECK-BE-NEXT: lxv vs6, 0(r4)
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; CHECK-BE-NEXT: addi r4, r4, 16
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; CHECK-BE-NEXT: xvf64gerpp acc0, vsp4, vs6
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; CHECK-BE-NEXT: bdnz .LBB1_2
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; CHECK-BE-NEXT: .LBB1_3: # %for.cond.cleanup
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; CHECK-BE-NEXT: xxmfacc acc0
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; CHECK-BE-NEXT: stxv vs0, 0(r3)
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; CHECK-BE-NEXT: stxv vs1, 16(r3)
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; CHECK-BE-NEXT: stxv vs2, 32(r3)
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; CHECK-BE-NEXT: stxv vs3, 48(r3)
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; CHECK-BE-NEXT: blr
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entry:
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%0 = load <16 x i8>, <16 x i8>* %Src, align 16
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%arrayidx1 = getelementptr inbounds <16 x i8>, <16 x i8>* %Src, i64 1
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%1 = load <16 x i8>, <16 x i8>* %arrayidx1, align 16
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%2 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %0, <16 x i8> %1)
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%arrayidx2 = getelementptr inbounds <16 x i8>, <16 x i8>* %Src, i64 2
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%3 = load <16 x i8>, <16 x i8>* %arrayidx2, align 16
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%4 = tail call <512 x i1> @llvm.ppc.mma.xvf64ger(<256 x i1> %2, <16 x i8> %3)
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%cmp14 = icmp sgt i32 %Len, 3
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br i1 %cmp14, label %for.body.preheader, label %for.cond.cleanup
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for.body.preheader:
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%wide.trip.count = zext i32 %Len to i64
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br label %for.body
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for.cond.cleanup:
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%Acc.0.lcssa = phi <512 x i1> [ %4, %entry ], [ %14, %for.body ]
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%5 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %Acc.0.lcssa)
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%6 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %5, 0
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store <16 x i8> %6, <16 x i8>* %Dst, align 16
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%7 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %5, 1
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%8 = getelementptr inbounds <16 x i8>, <16 x i8>* %Dst, i64 1
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store <16 x i8> %7, <16 x i8>* %8, align 16
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%9 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %5, 2
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%10 = getelementptr inbounds <16 x i8>, <16 x i8>* %Dst, i64 2
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store <16 x i8> %9, <16 x i8>* %10, align 16
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%11 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %5, 3
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%12 = getelementptr inbounds <16 x i8>, <16 x i8>* %Dst, i64 3
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store <16 x i8> %11, <16 x i8>* %12, align 16
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ret void
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for.body:
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%indvars.iv = phi i64 [ 3, %for.body.preheader ], [ %indvars.iv.next, %for.body ]
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%Acc.015 = phi <512 x i1> [ %4, %for.body.preheader ], [ %14, %for.body ]
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%arrayidx3 = getelementptr inbounds <16 x i8>, <16 x i8>* %Src, i64 %indvars.iv
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%13 = load <16 x i8>, <16 x i8>* %arrayidx3, align 16
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%14 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %Acc.015, <256 x i1> %2, <16 x i8> %13)
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
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br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
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}
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; This test uses an unprimed accumulator PHI node with two operands: an
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; implicitely defined unprimed accumulator and the unprimed result of the call
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; to xvf64gerpp. The compiler should replace this PHI node by a primed
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; accumulator PHI node.
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define void @testImplicitDef(<16 x i8>* %ptr) {
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; CHECK-LABEL: testImplicitDef:
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; CHECK: # %bb.0: # %label1
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; CHECK-NEXT: # implicit-def: $acc0
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; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB2_2
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; CHECK-NEXT: # %bb.1: # %label2
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; CHECK-NEXT: xvf64gerpp acc0, vsp0, vs0
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; CHECK-NEXT: .LBB2_2: # %label3
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; CHECK-NEXT: xxmfacc acc0
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; CHECK-NEXT: stxv vs0, 0(r3)
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: testImplicitDef:
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; CHECK-BE: # %bb.0: # %label1
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; CHECK-BE-NEXT: # implicit-def: $acc0
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; CHECK-BE-NEXT: bc 12, 4*cr5+lt, .LBB2_2
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; CHECK-BE-NEXT: # %bb.1: # %label2
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; CHECK-BE-NEXT: xvf64gerpp acc0, vsp0, vs0
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; CHECK-BE-NEXT: .LBB2_2: # %label3
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; CHECK-BE-NEXT: xxmfacc acc0
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; CHECK-BE-NEXT: stxv vs3, 0(r3)
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; CHECK-BE-NEXT: blr
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label1:
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br i1 undef, label %label3, label %label2
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label2:
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%0 = call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> undef, <256 x i1> undef, <16 x i8> undef)
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br label %label3
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label3:
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%1 = phi <512 x i1> [ undef, %label1 ], [ %0, %label2 ]
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%2 = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %1)
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%3 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %2, 3
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store <16 x i8> %3, <16 x i8>* %ptr, align 16
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ret void
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}
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; This test uses an unprimed accumulator PHI node with an unprimed accumulator
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; PHI node operand. The compiler should replace these PHI nodes by primed
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; accumulator PHI nodes.
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declare <512 x i1> @llvm.ppc.mma.xvf32gernp(<512 x i1>, <16 x i8>, <16 x i8>)
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define dso_local signext i32 @testNestedPHI(i32 signext %cond, i32 signext %count, <512 x i1>* nocapture %ptr, <16 x i8> %vc) {
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; CHECK-LABEL: testNestedPHI:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: cmplwi r3, 0
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; CHECK-NEXT: beq cr0, .LBB3_2
|
||
|
|
; CHECK-NEXT: # %bb.1: # %if.then
|
||
|
|
; CHECK-NEXT: xvf32gernp acc0, v2, v2
|
||
|
|
; CHECK-NEXT: cmpwi r4, 1
|
||
|
|
; CHECK-NEXT: bge cr0, .LBB3_3
|
||
|
|
; CHECK-NEXT: b .LBB3_5
|
||
|
|
; CHECK-NEXT: .LBB3_2:
|
||
|
|
; CHECK-NEXT: # implicit-def: $acc0
|
||
|
|
; CHECK-NEXT: cmpwi r4, 1
|
||
|
|
; CHECK-NEXT: blt cr0, .LBB3_5
|
||
|
|
; CHECK-NEXT: .LBB3_3: # %for.body.preheader
|
||
|
|
; CHECK-NEXT: clrldi r3, r4, 32
|
||
|
|
; CHECK-NEXT: mtctr r3
|
||
|
|
; CHECK-NEXT: .p2align 4
|
||
|
|
; CHECK-NEXT: .LBB3_4: # %for.body
|
||
|
|
; CHECK-NEXT: #
|
||
|
|
; CHECK-NEXT: xvf32gernp acc0, v2, v2
|
||
|
|
; CHECK-NEXT: bdnz .LBB3_4
|
||
|
|
; CHECK-NEXT: .LBB3_5: # %for.cond.cleanup
|
||
|
|
; CHECK-NEXT: li r3, 0
|
||
|
|
; CHECK-NEXT: xxmfacc acc0
|
||
|
|
; CHECK-NEXT: stxv vs0, 48(r5)
|
||
|
|
; CHECK-NEXT: stxv vs1, 32(r5)
|
||
|
|
; CHECK-NEXT: stxv vs2, 16(r5)
|
||
|
|
; CHECK-NEXT: stxv vs3, 0(r5)
|
||
|
|
; CHECK-NEXT: blr
|
||
|
|
;
|
||
|
|
; CHECK-BE-LABEL: testNestedPHI:
|
||
|
|
; CHECK-BE: # %bb.0: # %entry
|
||
|
|
; CHECK-BE-NEXT: cmplwi r3, 0
|
||
|
|
; CHECK-BE-NEXT: beq cr0, .LBB3_2
|
||
|
|
; CHECK-BE-NEXT: # %bb.1: # %if.then
|
||
|
|
; CHECK-BE-NEXT: xvf32gernp acc0, v2, v2
|
||
|
|
; CHECK-BE-NEXT: cmpwi r4, 1
|
||
|
|
; CHECK-BE-NEXT: bge cr0, .LBB3_3
|
||
|
|
; CHECK-BE-NEXT: b .LBB3_5
|
||
|
|
; CHECK-BE-NEXT: .LBB3_2:
|
||
|
|
; CHECK-BE-NEXT: # implicit-def: $acc0
|
||
|
|
; CHECK-BE-NEXT: cmpwi r4, 1
|
||
|
|
; CHECK-BE-NEXT: blt cr0, .LBB3_5
|
||
|
|
; CHECK-BE-NEXT: .LBB3_3: # %for.body.preheader
|
||
|
|
; CHECK-BE-NEXT: clrldi r3, r4, 32
|
||
|
|
; CHECK-BE-NEXT: mtctr r3
|
||
|
|
; CHECK-BE-NEXT: .p2align 4
|
||
|
|
; CHECK-BE-NEXT: .LBB3_4: # %for.body
|
||
|
|
; CHECK-BE-NEXT: #
|
||
|
|
; CHECK-BE-NEXT: xvf32gernp acc0, v2, v2
|
||
|
|
; CHECK-BE-NEXT: bdnz .LBB3_4
|
||
|
|
; CHECK-BE-NEXT: .LBB3_5: # %for.cond.cleanup
|
||
|
|
; CHECK-BE-NEXT: li r3, 0
|
||
|
|
; CHECK-BE-NEXT: xxmfacc acc0
|
||
|
|
; CHECK-BE-NEXT: stxv vs1, 16(r5)
|
||
|
|
; CHECK-BE-NEXT: stxv vs0, 0(r5)
|
||
|
|
; CHECK-BE-NEXT: stxv vs3, 48(r5)
|
||
|
|
; CHECK-BE-NEXT: stxv vs2, 32(r5)
|
||
|
|
; CHECK-BE-NEXT: blr
|
||
|
|
entry:
|
||
|
|
%tobool.not = icmp eq i32 %cond, 0
|
||
|
|
br i1 %tobool.not, label %if.end, label %if.then
|
||
|
|
|
||
|
|
if.then:
|
||
|
|
%0 = tail call <512 x i1> @llvm.ppc.mma.xvf32gernp(<512 x i1> undef, <16 x i8> %vc, <16 x i8> %vc)
|
||
|
|
br label %if.end
|
||
|
|
|
||
|
|
if.end:
|
||
|
|
%vq.0 = phi <512 x i1> [ %0, %if.then ], [ undef, %entry ]
|
||
|
|
%cmp9 = icmp sgt i32 %count, 0
|
||
|
|
br i1 %cmp9, label %for.body, label %for.cond.cleanup
|
||
|
|
|
||
|
|
for.cond.cleanup:
|
||
|
|
%vq.1.lcssa = phi <512 x i1> [ %vq.0, %if.end ], [ %1, %for.body ]
|
||
|
|
store <512 x i1> %vq.1.lcssa, <512 x i1>* %ptr, align 64
|
||
|
|
ret i32 0
|
||
|
|
|
||
|
|
for.body:
|
||
|
|
%i.011 = phi i32 [ %inc, %for.body ], [ 0, %if.end ]
|
||
|
|
%vq.110 = phi <512 x i1> [ %1, %for.body ], [ %vq.0, %if.end ]
|
||
|
|
%1 = tail call <512 x i1> @llvm.ppc.mma.xvf32gernp(<512 x i1> %vq.110, <16 x i8> %vc, <16 x i8> %vc)
|
||
|
|
%inc = add nuw nsw i32 %i.011, 1
|
||
|
|
%exitcond.not = icmp eq i32 %inc, %count
|
||
|
|
br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
|
||
|
|
}
|