35 lines
1.4 KiB
LLVM
35 lines
1.4 KiB
LLVM
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; RUN: llc < %s -march=nvptx -mcpu=sm_35 | FileCheck %s
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; Verify that we correctly emit code for extending ldg/ldu. We do not expose
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; extending variants in the backend, but the ldg/ldu selection code may pick
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; extending loads as candidates. We do want to support this, so make sure we
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; emit the necessary cvt.* instructions to implement the extension and let ptxas
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; emit the real extending loads.
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target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
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target triple = "nvptx64-nvidia-cuda"
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; CHECK-LABEL: spam
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define ptx_kernel void @spam(i8 addrspace(1)* noalias nocapture readonly %arg, i8 addrspace(1)* noalias nocapture %arg1, i64 %arg2, i64 %arg3) #0 {
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bb:
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%tmp = bitcast i8 addrspace(1)* %arg to i16 addrspace(1)*
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%tmp4 = bitcast i8 addrspace(1)* %arg1 to i64 addrspace(1)*
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%tmp5 = add nsw i64 %arg3, 8
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%tmp6 = getelementptr i16, i16 addrspace(1)* %tmp, i64 %tmp5
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; CHECK: ld.global.nc.u16
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%tmp7 = load i16, i16 addrspace(1)* %tmp6, align 2
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; CHECK: cvt.s32.s16
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%tmp8 = sext i16 %tmp7 to i64
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%tmp9 = mul nsw i64 %tmp8, %tmp8
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%tmp10 = load i64, i64 addrspace(1)* %tmp4, align 8
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%tmp11 = add nsw i64 %tmp9, %tmp10
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store i64 %tmp11, i64 addrspace(1)* %tmp4, align 8
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ret void
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}
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attributes #0 = { norecurse nounwind "polly.skip.fn" }
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!nvvm.annotations = !{!0}
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!0 = !{void (i8 addrspace(1)*, i8 addrspace(1)*, i64, i64)* @spam, !"maxntidx", i64 1, !"maxntidy", i64 1, !"maxntidz", i64 1}
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