59 lines
2.7 KiB
LLVM
59 lines
2.7 KiB
LLVM
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; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX %s
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; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX %s
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; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX-INV %s
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; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX-INV %s
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; RUN-TODO: llc -march=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX %s
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; RUN-TODO: llc -march=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX %s
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; RUN-TODO: llc -march=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX-INV,O32-FPXX-INV %s
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; RUN-TODO: llc -march=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX-INV,O32-FPXX-INV %s
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define void @fpu_clobber() nounwind {
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entry:
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call void asm "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f12},~{$f13},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
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ret void
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}
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; O32-FPXX-LABEL: fpu_clobber:
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; O32-FPXX-INV-NOT: sdc1 $f0,
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; O32-FPXX-INV-NOT: sdc1 $f1,
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; O32-FPXX-INV-NOT: sdc1 $f2,
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; O32-FPXX-INV-NOT: sdc1 $f3,
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; O32-FPXX-INV-NOT: sdc1 $f4,
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; O32-FPXX-INV-NOT: sdc1 $f5,
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; O32-FPXX-INV-NOT: sdc1 $f6,
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; O32-FPXX-INV-NOT: sdc1 $f7,
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; O32-FPXX-INV-NOT: sdc1 $f8,
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; O32-FPXX-INV-NOT: sdc1 $f9,
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; O32-FPXX-INV-NOT: sdc1 $f10,
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; O32-FPXX-INV-NOT: sdc1 $f11,
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; O32-FPXX-INV-NOT: sdc1 $f12,
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; O32-FPXX-INV-NOT: sdc1 $f13,
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; O32-FPXX-INV-NOT: sdc1 $f14,
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; O32-FPXX-INV-NOT: sdc1 $f15,
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; O32-FPXX-INV-NOT: sdc1 $f16,
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; O32-FPXX-INV-NOT: sdc1 $f17,
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; O32-FPXX-INV-NOT: sdc1 $f18,
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; O32-FPXX-INV-NOT: sdc1 $f19,
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; O32-FPXX-INV-NOT: sdc1 $f21,
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; O32-FPXX-INV-NOT: sdc1 $f23,
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; O32-FPXX-INV-NOT: sdc1 $f25,
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; O32-FPXX-INV-NOT: sdc1 $f27,
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; O32-FPXX-INV-NOT: sdc1 $f29,
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; O32-FPXX-INV-NOT: sdc1 $f31,
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; O32-FPXX: addiu $sp, $sp, -48
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; O32-FPXX-DAG: sdc1 [[F20:\$f20]], [[OFF20:[0-9]+]]($sp)
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; O32-FPXX-DAG: sdc1 [[F22:\$f22]], [[OFF22:[0-9]+]]($sp)
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; O32-FPXX-DAG: sdc1 [[F24:\$f24]], [[OFF24:[0-9]+]]($sp)
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; O32-FPXX-DAG: sdc1 [[F26:\$f26]], [[OFF26:[0-9]+]]($sp)
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; O32-FPXX-DAG: sdc1 [[F28:\$f28]], [[OFF28:[0-9]+]]($sp)
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; O32-FPXX-DAG: sdc1 [[F30:\$f30]], [[OFF30:[0-9]+]]($sp)
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; O32-FPXX-DAG: ldc1 [[F20]], [[OFF20]]($sp)
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; O32-FPXX-DAG: ldc1 [[F22]], [[OFF22]]($sp)
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; O32-FPXX-DAG: ldc1 [[F24]], [[OFF24]]($sp)
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; O32-FPXX-DAG: ldc1 [[F26]], [[OFF26]]($sp)
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; O32-FPXX-DAG: ldc1 [[F28]], [[OFF28]]($sp)
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; O32-FPXX-DAG: ldc1 [[F30]], [[OFF30]]($sp)
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; O32-FPXX: addiu $sp, $sp, 48
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