241 lines
7.5 KiB
Plaintext
241 lines
7.5 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=mips-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
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--- |
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define void @load1_s8_to_zextLoad1_s32(i8* %px) {entry: ret void}
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define void @load2_s16_to_zextLoad2_s32(i16* %px) {entry: ret void}
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define void @load1_s8_to_zextLoad1_s16(i8* %px) {entry: ret void}
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define void @load1_s8_to_zextLoad1_s16_to_zextLoad1_s32(i8* %px) {entry: ret void}
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define void @load4_s32_to_zextLoad4_s64(i8* %px) {entry: ret void}
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define void @load1_s8_to_sextLoad1_s32(i8* %px) {entry: ret void}
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define void @load2_s16_to_sextLoad2_s32(i16* %px) {entry: ret void}
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define void @load1_s8_to_sextLoad1_s16(i8* %px) {entry: ret void}
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define void @load1_s8_to_sextLoad1_s16_to_sextLoad1_s32(i8* %px) {entry: ret void}
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define void @load4_s32_to_sextLoad4_s64(i8* %px) {entry: ret void}
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...
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---
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name: load1_s8_to_zextLoad1_s32
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s32
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
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; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px)
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; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
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; MIPS32: RetRA implicit $v0
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%0:_(p0) = COPY $a0
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%1:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.px)
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%2:_(s32) = G_ZEXT %1(s8)
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: load2_s16_to_zextLoad2_s32
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: load2_s16_to_zextLoad2_s32
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
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; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 2 from %ir.px)
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; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
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; MIPS32: RetRA implicit $v0
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%0:_(p0) = COPY $a0
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%1:_(s16) = G_LOAD %0(p0) :: (load 2 from %ir.px)
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%2:_(s32) = G_ZEXT %1(s16)
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: load1_s8_to_zextLoad1_s16
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s16
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
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; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s16) = G_ZEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px)
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; MIPS32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXTLOAD]](s16)
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; MIPS32: $v0 = COPY [[ANYEXT]](s32)
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; MIPS32: RetRA implicit $v0
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%0:_(p0) = COPY $a0
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%1:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.px)
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%2:_(s16) = G_ZEXT %1(s8)
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%3:_(s32) = G_ANYEXT %2(s16)
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$v0 = COPY %3(s32)
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RetRA implicit $v0
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...
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---
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name: load1_s8_to_zextLoad1_s16_to_zextLoad1_s32
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s16_to_zextLoad1_s32
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
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; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px)
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; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
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; MIPS32: RetRA implicit $v0
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%0:_(p0) = COPY $a0
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%1:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.px)
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%2:_(s16) = G_ZEXT %1(s8)
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%3:_(s32) = G_ZEXT %2(s16)
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$v0 = COPY %3(s32)
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RetRA implicit $v0
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...
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---
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name: load4_s32_to_zextLoad4_s64
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: load4_s32_to_zextLoad4_s64
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
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; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load 4 from %ir.px)
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; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ZEXTLOAD]](s64)
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; MIPS32: $v0 = COPY [[UV]](s32)
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; MIPS32: $v1 = COPY [[UV1]](s32)
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; MIPS32: RetRA implicit $v0, implicit $v1
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%0:_(p0) = COPY $a0
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%1:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.px)
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%2:_(s64) = G_ZEXT %1(s32)
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%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
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$v0 = COPY %3(s32)
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$v1 = COPY %4(s32)
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RetRA implicit $v0, implicit $v1
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...
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---
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name: load1_s8_to_sextLoad1_s32
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s32
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
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; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px)
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; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
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; MIPS32: RetRA implicit $v0
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%0:_(p0) = COPY $a0
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%1:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.px)
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%2:_(s32) = G_SEXT %1(s8)
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: load2_s16_to_sextLoad2_s32
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: load2_s16_to_sextLoad2_s32
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
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; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 2 from %ir.px)
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; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
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; MIPS32: RetRA implicit $v0
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%0:_(p0) = COPY $a0
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%1:_(s16) = G_LOAD %0(p0) :: (load 2 from %ir.px)
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%2:_(s32) = G_SEXT %1(s16)
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: load1_s8_to_sextLoad1_s16
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s16
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
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; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s16) = G_SEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px)
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; MIPS32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SEXTLOAD]](s16)
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; MIPS32: $v0 = COPY [[ANYEXT]](s32)
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; MIPS32: RetRA implicit $v0
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%0:_(p0) = COPY $a0
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%1:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.px)
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%2:_(s16) = G_SEXT %1(s8)
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%3:_(s32) = G_ANYEXT %2(s16)
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$v0 = COPY %3(s32)
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RetRA implicit $v0
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...
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---
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name: load1_s8_to_sextLoad1_s16_to_sextLoad1_s32
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s16_to_sextLoad1_s32
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
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; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1 from %ir.px)
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; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
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; MIPS32: RetRA implicit $v0
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%0:_(p0) = COPY $a0
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%1:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.px)
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%2:_(s16) = G_SEXT %1(s8)
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%3:_(s32) = G_SEXT %2(s16)
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$v0 = COPY %3(s32)
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RetRA implicit $v0
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...
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---
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name: load4_s32_to_sextLoad4_s64
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: load4_s32_to_sextLoad4_s64
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
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; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load 4 from %ir.px)
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; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SEXTLOAD]](s64)
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; MIPS32: $v0 = COPY [[UV]](s32)
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; MIPS32: $v1 = COPY [[UV1]](s32)
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; MIPS32: RetRA implicit $v0, implicit $v1
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%0:_(p0) = COPY $a0
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%1:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.px)
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%2:_(s64) = G_SEXT %1(s32)
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%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
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$v0 = COPY %3(s32)
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$v1 = COPY %4(s32)
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RetRA implicit $v0, implicit $v1
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...
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