75 lines
2.7 KiB
LLVM
75 lines
2.7 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=P5600
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declare <16 x i8> @llvm.mips.mulv.b(<16 x i8>, <16 x i8>)
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define void @mul_v16i8_builtin(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) {
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; P5600-LABEL: mul_v16i8_builtin:
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; P5600: # %bb.0: # %entry
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; P5600-NEXT: ld.b $w0, 0($4)
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; P5600-NEXT: ld.b $w1, 0($5)
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; P5600-NEXT: mulv.b $w0, $w0, $w1
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; P5600-NEXT: st.b $w0, 0($6)
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; P5600-NEXT: jr $ra
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; P5600-NEXT: nop
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entry:
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%0 = load <16 x i8>, <16 x i8>* %a, align 16
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%1 = load <16 x i8>, <16 x i8>* %b, align 16
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%2 = tail call <16 x i8> @llvm.mips.mulv.b(<16 x i8> %0, <16 x i8> %1)
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store <16 x i8> %2, <16 x i8>* %c, align 16
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ret void
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}
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declare <8 x i16> @llvm.mips.mulv.h(<8 x i16>, <8 x i16>)
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define void @mul_v8i16_builtin(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) {
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; P5600-LABEL: mul_v8i16_builtin:
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; P5600: # %bb.0: # %entry
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; P5600-NEXT: ld.h $w0, 0($4)
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; P5600-NEXT: ld.h $w1, 0($5)
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; P5600-NEXT: mulv.h $w0, $w0, $w1
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; P5600-NEXT: st.h $w0, 0($6)
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; P5600-NEXT: jr $ra
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; P5600-NEXT: nop
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entry:
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%0 = load <8 x i16>, <8 x i16>* %a, align 16
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%1 = load <8 x i16>, <8 x i16>* %b, align 16
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%2 = tail call <8 x i16> @llvm.mips.mulv.h(<8 x i16> %0, <8 x i16> %1)
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store <8 x i16> %2, <8 x i16>* %c, align 16
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ret void
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}
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declare <4 x i32> @llvm.mips.mulv.w(<4 x i32>, <4 x i32>)
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define void @mul_v4i32_builtin(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) {
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; P5600-LABEL: mul_v4i32_builtin:
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; P5600: # %bb.0: # %entry
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; P5600-NEXT: ld.w $w0, 0($4)
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; P5600-NEXT: ld.w $w1, 0($5)
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; P5600-NEXT: mulv.w $w0, $w0, $w1
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; P5600-NEXT: st.w $w0, 0($6)
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; P5600-NEXT: jr $ra
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; P5600-NEXT: nop
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entry:
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%0 = load <4 x i32>, <4 x i32>* %a, align 16
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%1 = load <4 x i32>, <4 x i32>* %b, align 16
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%2 = tail call <4 x i32> @llvm.mips.mulv.w(<4 x i32> %0, <4 x i32> %1)
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store <4 x i32> %2, <4 x i32>* %c, align 16
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ret void
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}
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declare <2 x i64> @llvm.mips.mulv.d(<2 x i64>, <2 x i64>)
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define void @mul_v2i64_builtin(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) {
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; P5600-LABEL: mul_v2i64_builtin:
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; P5600: # %bb.0: # %entry
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; P5600-NEXT: ld.d $w0, 0($4)
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; P5600-NEXT: ld.d $w1, 0($5)
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; P5600-NEXT: mulv.d $w0, $w0, $w1
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; P5600-NEXT: st.d $w0, 0($6)
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; P5600-NEXT: jr $ra
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; P5600-NEXT: nop
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entry:
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%0 = load <2 x i64>, <2 x i64>* %a, align 16
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%1 = load <2 x i64>, <2 x i64>* %b, align 16
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%2 = tail call <2 x i64> @llvm.mips.mulv.d(<2 x i64> %0, <2 x i64> %1)
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store <2 x i64> %2, <2 x i64>* %c, align 16
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ret void
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}
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