543 lines
19 KiB
Plaintext
543 lines
19 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
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--- |
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define void @sdiv_i8() {entry: ret void}
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define void @sdiv_i16() {entry: ret void}
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define void @sdiv_i32() {entry: ret void}
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define void @sdiv_i64() {entry: ret void}
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define void @srem_i8() {entry: ret void}
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define void @srem_i16() {entry: ret void}
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define void @srem_i32() {entry: ret void}
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define void @srem_i64() {entry: ret void}
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define void @udiv_i8() {entry: ret void}
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define void @udiv_i16() {entry: ret void}
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define void @udiv_i32() {entry: ret void}
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define void @udiv_i64() {entry: ret void}
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define void @urem_i8() {entry: ret void}
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define void @urem_i16() {entry: ret void}
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define void @urem_i32() {entry: ret void}
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define void @urem_i64() {entry: ret void}
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...
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---
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name: sdiv_i8
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: sdiv_i8
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
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; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
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; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
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; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
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; MIPS32: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
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; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
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; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
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; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
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; MIPS32: $v0 = COPY [[ASHR2]](s32)
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; MIPS32: RetRA implicit $v0
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%2:_(s32) = COPY $a0
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%0:_(s8) = G_TRUNC %2(s32)
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%3:_(s32) = COPY $a1
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%1:_(s8) = G_TRUNC %3(s32)
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%4:_(s8) = G_SDIV %1, %0
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%5:_(s32) = G_SEXT %4(s8)
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$v0 = COPY %5(s32)
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RetRA implicit $v0
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...
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---
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name: sdiv_i16
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: sdiv_i16
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
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; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
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; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
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; MIPS32: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
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; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
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; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
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; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
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; MIPS32: $v0 = COPY [[ASHR2]](s32)
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; MIPS32: RetRA implicit $v0
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%2:_(s32) = COPY $a0
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%0:_(s16) = G_TRUNC %2(s32)
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%3:_(s32) = COPY $a1
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%1:_(s16) = G_TRUNC %3(s32)
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%4:_(s16) = G_SDIV %1, %0
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%5:_(s32) = G_SEXT %4(s16)
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$v0 = COPY %5(s32)
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RetRA implicit $v0
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...
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---
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name: sdiv_i32
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: sdiv_i32
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[COPY1]], [[COPY]]
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; MIPS32: $v0 = COPY [[SDIV]](s32)
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; MIPS32: RetRA implicit $v0
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%0:_(s32) = COPY $a0
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%1:_(s32) = COPY $a1
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%2:_(s32) = G_SDIV %1, %0
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: sdiv_i64
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1, $a2, $a3
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; MIPS32-LABEL: name: sdiv_i64
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; MIPS32: liveins: $a0, $a1, $a2, $a3
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
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; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
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; MIPS32: $a0 = COPY [[COPY2]](s32)
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; MIPS32: $a1 = COPY [[COPY3]](s32)
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; MIPS32: $a2 = COPY [[COPY]](s32)
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; MIPS32: $a3 = COPY [[COPY1]](s32)
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; MIPS32: JAL &__divdi3, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0, implicit-def $v1
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; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY $v0
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; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY $v1
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; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
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; MIPS32: $v0 = COPY [[COPY4]](s32)
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; MIPS32: $v1 = COPY [[COPY5]](s32)
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; MIPS32: RetRA implicit $v0, implicit $v1
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%2:_(s32) = COPY $a0
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%3:_(s32) = COPY $a1
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%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
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%4:_(s32) = COPY $a2
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%5:_(s32) = COPY $a3
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%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
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%6:_(s64) = G_SDIV %1, %0
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%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
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$v0 = COPY %7(s32)
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$v1 = COPY %8(s32)
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RetRA implicit $v0, implicit $v1
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...
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---
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name: srem_i8
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: srem_i8
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
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; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
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; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
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; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
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; MIPS32: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]]
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; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32)
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; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
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; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
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; MIPS32: $v0 = COPY [[ASHR2]](s32)
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; MIPS32: RetRA implicit $v0
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%2:_(s32) = COPY $a0
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%0:_(s8) = G_TRUNC %2(s32)
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%3:_(s32) = COPY $a1
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%1:_(s8) = G_TRUNC %3(s32)
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%4:_(s8) = G_SREM %1, %0
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%5:_(s32) = G_SEXT %4(s8)
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$v0 = COPY %5(s32)
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RetRA implicit $v0
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...
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---
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name: srem_i16
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: srem_i16
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
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; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
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; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
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; MIPS32: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]]
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; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32)
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; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
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; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
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; MIPS32: $v0 = COPY [[ASHR2]](s32)
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; MIPS32: RetRA implicit $v0
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%2:_(s32) = COPY $a0
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%0:_(s16) = G_TRUNC %2(s32)
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%3:_(s32) = COPY $a1
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%1:_(s16) = G_TRUNC %3(s32)
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%4:_(s16) = G_SREM %1, %0
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%5:_(s32) = G_SEXT %4(s16)
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$v0 = COPY %5(s32)
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RetRA implicit $v0
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...
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---
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name: srem_i32
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: srem_i32
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[COPY1]], [[COPY]]
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; MIPS32: $v0 = COPY [[SREM]](s32)
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; MIPS32: RetRA implicit $v0
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%0:_(s32) = COPY $a0
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%1:_(s32) = COPY $a1
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%2:_(s32) = G_SREM %1, %0
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: srem_i64
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1, $a2, $a3
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; MIPS32-LABEL: name: srem_i64
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; MIPS32: liveins: $a0, $a1, $a2, $a3
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
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; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
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; MIPS32: $a0 = COPY [[COPY2]](s32)
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; MIPS32: $a1 = COPY [[COPY3]](s32)
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; MIPS32: $a2 = COPY [[COPY]](s32)
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; MIPS32: $a3 = COPY [[COPY1]](s32)
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; MIPS32: JAL &__moddi3, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0, implicit-def $v1
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; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY $v0
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; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY $v1
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; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
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||
|
|
; MIPS32: $v0 = COPY [[COPY4]](s32)
|
||
|
|
; MIPS32: $v1 = COPY [[COPY5]](s32)
|
||
|
|
; MIPS32: RetRA implicit $v0, implicit $v1
|
||
|
|
%2:_(s32) = COPY $a0
|
||
|
|
%3:_(s32) = COPY $a1
|
||
|
|
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
|
||
|
|
%4:_(s32) = COPY $a2
|
||
|
|
%5:_(s32) = COPY $a3
|
||
|
|
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
|
||
|
|
%6:_(s64) = G_SREM %1, %0
|
||
|
|
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
|
||
|
|
$v0 = COPY %7(s32)
|
||
|
|
$v1 = COPY %8(s32)
|
||
|
|
RetRA implicit $v0, implicit $v1
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: udiv_i8
|
||
|
|
alignment: 4
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.1.entry:
|
||
|
|
liveins: $a0, $a1
|
||
|
|
|
||
|
|
; MIPS32-LABEL: name: udiv_i8
|
||
|
|
; MIPS32: liveins: $a0, $a1
|
||
|
|
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
|
||
|
|
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
|
||
|
|
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
|
||
|
|
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
|
||
|
|
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
|
||
|
|
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
|
||
|
|
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
|
||
|
|
; MIPS32: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
|
||
|
|
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UDIV]](s32)
|
||
|
|
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
|
||
|
|
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C1]](s32)
|
||
|
|
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
|
||
|
|
; MIPS32: $v0 = COPY [[ASHR]](s32)
|
||
|
|
; MIPS32: RetRA implicit $v0
|
||
|
|
%2:_(s32) = COPY $a0
|
||
|
|
%0:_(s8) = G_TRUNC %2(s32)
|
||
|
|
%3:_(s32) = COPY $a1
|
||
|
|
%1:_(s8) = G_TRUNC %3(s32)
|
||
|
|
%4:_(s8) = G_UDIV %1, %0
|
||
|
|
%5:_(s32) = G_SEXT %4(s8)
|
||
|
|
$v0 = COPY %5(s32)
|
||
|
|
RetRA implicit $v0
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: udiv_i16
|
||
|
|
alignment: 4
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.1.entry:
|
||
|
|
liveins: $a0, $a1
|
||
|
|
|
||
|
|
; MIPS32-LABEL: name: udiv_i16
|
||
|
|
; MIPS32: liveins: $a0, $a1
|
||
|
|
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
|
||
|
|
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
|
||
|
|
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
|
||
|
|
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
|
||
|
|
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
|
||
|
|
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
|
||
|
|
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
|
||
|
|
; MIPS32: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
|
||
|
|
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UDIV]](s32)
|
||
|
|
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
|
||
|
|
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C1]](s32)
|
||
|
|
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
|
||
|
|
; MIPS32: $v0 = COPY [[ASHR]](s32)
|
||
|
|
; MIPS32: RetRA implicit $v0
|
||
|
|
%2:_(s32) = COPY $a0
|
||
|
|
%0:_(s16) = G_TRUNC %2(s32)
|
||
|
|
%3:_(s32) = COPY $a1
|
||
|
|
%1:_(s16) = G_TRUNC %3(s32)
|
||
|
|
%4:_(s16) = G_UDIV %1, %0
|
||
|
|
%5:_(s32) = G_SEXT %4(s16)
|
||
|
|
$v0 = COPY %5(s32)
|
||
|
|
RetRA implicit $v0
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: udiv_i32
|
||
|
|
alignment: 4
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.1.entry:
|
||
|
|
liveins: $a0, $a1
|
||
|
|
|
||
|
|
; MIPS32-LABEL: name: udiv_i32
|
||
|
|
; MIPS32: liveins: $a0, $a1
|
||
|
|
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
|
||
|
|
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
|
||
|
|
; MIPS32: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[COPY1]], [[COPY]]
|
||
|
|
; MIPS32: $v0 = COPY [[UDIV]](s32)
|
||
|
|
; MIPS32: RetRA implicit $v0
|
||
|
|
%0:_(s32) = COPY $a0
|
||
|
|
%1:_(s32) = COPY $a1
|
||
|
|
%2:_(s32) = G_UDIV %1, %0
|
||
|
|
$v0 = COPY %2(s32)
|
||
|
|
RetRA implicit $v0
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: udiv_i64
|
||
|
|
alignment: 4
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.1.entry:
|
||
|
|
liveins: $a0, $a1, $a2, $a3
|
||
|
|
|
||
|
|
; MIPS32-LABEL: name: udiv_i64
|
||
|
|
; MIPS32: liveins: $a0, $a1, $a2, $a3
|
||
|
|
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
|
||
|
|
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
|
||
|
|
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
|
||
|
|
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
|
||
|
|
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
|
||
|
|
; MIPS32: $a0 = COPY [[COPY2]](s32)
|
||
|
|
; MIPS32: $a1 = COPY [[COPY3]](s32)
|
||
|
|
; MIPS32: $a2 = COPY [[COPY]](s32)
|
||
|
|
; MIPS32: $a3 = COPY [[COPY1]](s32)
|
||
|
|
; MIPS32: JAL &__udivdi3, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0, implicit-def $v1
|
||
|
|
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY $v0
|
||
|
|
; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY $v1
|
||
|
|
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
|
||
|
|
; MIPS32: $v0 = COPY [[COPY4]](s32)
|
||
|
|
; MIPS32: $v1 = COPY [[COPY5]](s32)
|
||
|
|
; MIPS32: RetRA implicit $v0, implicit $v1
|
||
|
|
%2:_(s32) = COPY $a0
|
||
|
|
%3:_(s32) = COPY $a1
|
||
|
|
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
|
||
|
|
%4:_(s32) = COPY $a2
|
||
|
|
%5:_(s32) = COPY $a3
|
||
|
|
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
|
||
|
|
%6:_(s64) = G_UDIV %1, %0
|
||
|
|
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
|
||
|
|
$v0 = COPY %7(s32)
|
||
|
|
$v1 = COPY %8(s32)
|
||
|
|
RetRA implicit $v0, implicit $v1
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: urem_i8
|
||
|
|
alignment: 4
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.1.entry:
|
||
|
|
liveins: $a0, $a1
|
||
|
|
|
||
|
|
; MIPS32-LABEL: name: urem_i8
|
||
|
|
; MIPS32: liveins: $a0, $a1
|
||
|
|
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
|
||
|
|
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
|
||
|
|
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
|
||
|
|
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
|
||
|
|
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
|
||
|
|
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
|
||
|
|
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
|
||
|
|
; MIPS32: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[AND]], [[AND1]]
|
||
|
|
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UREM]](s32)
|
||
|
|
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
|
||
|
|
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C1]](s32)
|
||
|
|
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
|
||
|
|
; MIPS32: $v0 = COPY [[ASHR]](s32)
|
||
|
|
; MIPS32: RetRA implicit $v0
|
||
|
|
%2:_(s32) = COPY $a0
|
||
|
|
%0:_(s8) = G_TRUNC %2(s32)
|
||
|
|
%3:_(s32) = COPY $a1
|
||
|
|
%1:_(s8) = G_TRUNC %3(s32)
|
||
|
|
%4:_(s8) = G_UREM %1, %0
|
||
|
|
%5:_(s32) = G_SEXT %4(s8)
|
||
|
|
$v0 = COPY %5(s32)
|
||
|
|
RetRA implicit $v0
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: urem_i16
|
||
|
|
alignment: 4
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.1.entry:
|
||
|
|
liveins: $a0, $a1
|
||
|
|
|
||
|
|
; MIPS32-LABEL: name: urem_i16
|
||
|
|
; MIPS32: liveins: $a0, $a1
|
||
|
|
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
|
||
|
|
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
|
||
|
|
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
|
||
|
|
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
|
||
|
|
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
|
||
|
|
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
|
||
|
|
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
|
||
|
|
; MIPS32: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[AND]], [[AND1]]
|
||
|
|
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UREM]](s32)
|
||
|
|
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
|
||
|
|
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C1]](s32)
|
||
|
|
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
|
||
|
|
; MIPS32: $v0 = COPY [[ASHR]](s32)
|
||
|
|
; MIPS32: RetRA implicit $v0
|
||
|
|
%2:_(s32) = COPY $a0
|
||
|
|
%0:_(s16) = G_TRUNC %2(s32)
|
||
|
|
%3:_(s32) = COPY $a1
|
||
|
|
%1:_(s16) = G_TRUNC %3(s32)
|
||
|
|
%4:_(s16) = G_UREM %1, %0
|
||
|
|
%5:_(s32) = G_SEXT %4(s16)
|
||
|
|
$v0 = COPY %5(s32)
|
||
|
|
RetRA implicit $v0
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: urem_i32
|
||
|
|
alignment: 4
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.1.entry:
|
||
|
|
liveins: $a0, $a1
|
||
|
|
|
||
|
|
; MIPS32-LABEL: name: urem_i32
|
||
|
|
; MIPS32: liveins: $a0, $a1
|
||
|
|
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
|
||
|
|
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
|
||
|
|
; MIPS32: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[COPY1]], [[COPY]]
|
||
|
|
; MIPS32: $v0 = COPY [[UREM]](s32)
|
||
|
|
; MIPS32: RetRA implicit $v0
|
||
|
|
%0:_(s32) = COPY $a0
|
||
|
|
%1:_(s32) = COPY $a1
|
||
|
|
%2:_(s32) = G_UREM %1, %0
|
||
|
|
$v0 = COPY %2(s32)
|
||
|
|
RetRA implicit $v0
|
||
|
|
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: urem_i64
|
||
|
|
alignment: 4
|
||
|
|
tracksRegLiveness: true
|
||
|
|
body: |
|
||
|
|
bb.1.entry:
|
||
|
|
liveins: $a0, $a1, $a2, $a3
|
||
|
|
|
||
|
|
; MIPS32-LABEL: name: urem_i64
|
||
|
|
; MIPS32: liveins: $a0, $a1, $a2, $a3
|
||
|
|
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
|
||
|
|
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
|
||
|
|
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
|
||
|
|
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
|
||
|
|
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
|
||
|
|
; MIPS32: $a0 = COPY [[COPY2]](s32)
|
||
|
|
; MIPS32: $a1 = COPY [[COPY3]](s32)
|
||
|
|
; MIPS32: $a2 = COPY [[COPY]](s32)
|
||
|
|
; MIPS32: $a3 = COPY [[COPY1]](s32)
|
||
|
|
; MIPS32: JAL &__umoddi3, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2, implicit $a3, implicit-def $v0, implicit-def $v1
|
||
|
|
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY $v0
|
||
|
|
; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY $v1
|
||
|
|
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
|
||
|
|
; MIPS32: $v0 = COPY [[COPY4]](s32)
|
||
|
|
; MIPS32: $v1 = COPY [[COPY5]](s32)
|
||
|
|
; MIPS32: RetRA implicit $v0, implicit $v1
|
||
|
|
%2:_(s32) = COPY $a0
|
||
|
|
%3:_(s32) = COPY $a1
|
||
|
|
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
|
||
|
|
%4:_(s32) = COPY $a2
|
||
|
|
%5:_(s32) = COPY $a3
|
||
|
|
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
|
||
|
|
%6:_(s64) = G_UREM %1, %0
|
||
|
|
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
|
||
|
|
$v0 = COPY %7(s32)
|
||
|
|
$v1 = COPY %8(s32)
|
||
|
|
RetRA implicit $v0, implicit $v1
|
||
|
|
|
||
|
|
...
|