216 lines
12 KiB
Plaintext
216 lines
12 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
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# RUN: llc -mtriple=mipsel-linux-gnu -run-pass=legalizer -mattr=+mips32r2 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R2
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--- |
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define void @bitreverse_i32() { entry: ret void }
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define void @bitreverse_i64() { entry: ret void }
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...
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---
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name: bitreverse_i32
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: bitreverse_i32
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
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; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
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; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
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; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
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; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65280
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; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
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; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C2]](s32)
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; MIPS32: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
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; MIPS32: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
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; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
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; MIPS32: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[AND1]]
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; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
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; MIPS32: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -252645136
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; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[OR2]], [[C4]]
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; MIPS32: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C3]](s32)
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; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR2]], [[C3]](s32)
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; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C4]]
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; MIPS32: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[AND3]]
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; MIPS32: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
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; MIPS32: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 -858993460
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; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[OR3]], [[C6]]
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; MIPS32: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[C5]](s32)
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; MIPS32: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[OR3]], [[C5]](s32)
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; MIPS32: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SHL3]], [[C6]]
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; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND5]]
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; MIPS32: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; MIPS32: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1431655766
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; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]]
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; MIPS32: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[C7]](s32)
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; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32)
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; MIPS32: [[AND7:%[0-9]+]]:_(s32) = G_AND [[SHL4]], [[C8]]
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; MIPS32: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[AND7]]
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; MIPS32: $v0 = COPY [[OR5]](s32)
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; MIPS32: RetRA implicit $v0
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; MIPS32R2-LABEL: name: bitreverse_i32
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; MIPS32R2: liveins: $a0
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; MIPS32R2: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32R2: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
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; MIPS32R2: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
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; MIPS32R2: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -252645136
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; MIPS32R2: [[AND:%[0-9]+]]:_(s32) = G_AND [[BSWAP]], [[C1]]
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; MIPS32R2: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32)
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; MIPS32R2: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BSWAP]], [[C]](s32)
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; MIPS32R2: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C1]]
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; MIPS32R2: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[AND1]]
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; MIPS32R2: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
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; MIPS32R2: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -858993460
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; MIPS32R2: [[AND2:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C3]]
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; MIPS32R2: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C2]](s32)
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; MIPS32R2: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[OR]], [[C2]](s32)
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; MIPS32R2: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SHL1]], [[C3]]
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; MIPS32R2: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[AND3]]
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; MIPS32R2: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; MIPS32R2: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1431655766
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; MIPS32R2: [[AND4:%[0-9]+]]:_(s32) = G_AND [[OR1]], [[C5]]
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; MIPS32R2: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[C4]](s32)
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; MIPS32R2: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C4]](s32)
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; MIPS32R2: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C5]]
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; MIPS32R2: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[AND5]]
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; MIPS32R2: $v0 = COPY [[OR2]](s32)
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; MIPS32R2: RetRA implicit $v0
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%0:_(s32) = COPY $a0
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%1:_(s32) = G_BITREVERSE %0
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$v0 = COPY %1(s32)
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RetRA implicit $v0
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...
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---
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name: bitreverse_i64
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: bitreverse_i64
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
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; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
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; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
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; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
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; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65280
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; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
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; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C2]](s32)
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; MIPS32: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
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; MIPS32: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
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; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
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; MIPS32: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[AND1]]
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; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
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; MIPS32: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -252645136
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; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[OR2]], [[C4]]
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; MIPS32: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C3]](s32)
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; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR2]], [[C3]](s32)
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; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C4]]
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; MIPS32: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[AND3]]
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; MIPS32: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
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; MIPS32: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 -858993460
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; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[OR3]], [[C6]]
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; MIPS32: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[C5]](s32)
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; MIPS32: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[OR3]], [[C5]](s32)
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; MIPS32: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SHL3]], [[C6]]
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; MIPS32: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND5]]
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; MIPS32: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; MIPS32: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1431655766
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; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C8]]
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; MIPS32: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[C7]](s32)
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; MIPS32: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C7]](s32)
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; MIPS32: [[AND7:%[0-9]+]]:_(s32) = G_AND [[SHL4]], [[C8]]
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; MIPS32: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[AND7]]
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; MIPS32: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
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; MIPS32: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
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; MIPS32: [[OR6:%[0-9]+]]:_(s32) = G_OR [[LSHR5]], [[SHL5]]
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; MIPS32: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
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; MIPS32: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C2]](s32)
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; MIPS32: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL6]]
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; MIPS32: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
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; MIPS32: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C1]]
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; MIPS32: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[AND9]]
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; MIPS32: [[AND10:%[0-9]+]]:_(s32) = G_AND [[OR8]], [[C4]]
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; MIPS32: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[C3]](s32)
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; MIPS32: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[OR8]], [[C3]](s32)
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; MIPS32: [[AND11:%[0-9]+]]:_(s32) = G_AND [[SHL7]], [[C4]]
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; MIPS32: [[OR9:%[0-9]+]]:_(s32) = G_OR [[LSHR7]], [[AND11]]
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; MIPS32: [[AND12:%[0-9]+]]:_(s32) = G_AND [[OR9]], [[C6]]
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; MIPS32: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND12]], [[C5]](s32)
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; MIPS32: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[OR9]], [[C5]](s32)
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; MIPS32: [[AND13:%[0-9]+]]:_(s32) = G_AND [[SHL8]], [[C6]]
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; MIPS32: [[OR10:%[0-9]+]]:_(s32) = G_OR [[LSHR8]], [[AND13]]
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; MIPS32: [[AND14:%[0-9]+]]:_(s32) = G_AND [[OR10]], [[C8]]
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; MIPS32: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND14]], [[C7]](s32)
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; MIPS32: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[OR10]], [[C7]](s32)
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; MIPS32: [[AND15:%[0-9]+]]:_(s32) = G_AND [[SHL9]], [[C8]]
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; MIPS32: [[OR11:%[0-9]+]]:_(s32) = G_OR [[LSHR9]], [[AND15]]
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; MIPS32: $v0 = COPY [[OR5]](s32)
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; MIPS32: $v1 = COPY [[OR11]](s32)
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; MIPS32: RetRA implicit $v0, implicit $v1
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; MIPS32R2-LABEL: name: bitreverse_i64
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; MIPS32R2: liveins: $a0, $a1
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; MIPS32R2: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32R2: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32R2: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY1]]
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; MIPS32R2: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
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; MIPS32R2: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -252645136
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; MIPS32R2: [[AND:%[0-9]+]]:_(s32) = G_AND [[BSWAP]], [[C1]]
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; MIPS32R2: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32)
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; MIPS32R2: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BSWAP]], [[C]](s32)
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; MIPS32R2: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C1]]
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; MIPS32R2: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[AND1]]
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; MIPS32R2: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
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; MIPS32R2: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -858993460
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; MIPS32R2: [[AND2:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C3]]
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; MIPS32R2: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C2]](s32)
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; MIPS32R2: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[OR]], [[C2]](s32)
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; MIPS32R2: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SHL1]], [[C3]]
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; MIPS32R2: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[AND3]]
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; MIPS32R2: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; MIPS32R2: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1431655766
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; MIPS32R2: [[AND4:%[0-9]+]]:_(s32) = G_AND [[OR1]], [[C5]]
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; MIPS32R2: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[C4]](s32)
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; MIPS32R2: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR1]], [[C4]](s32)
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; MIPS32R2: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C5]]
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; MIPS32R2: [[OR2:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[AND5]]
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; MIPS32R2: [[BSWAP1:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
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; MIPS32R2: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BSWAP1]], [[C1]]
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; MIPS32R2: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[C]](s32)
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; MIPS32R2: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[BSWAP1]], [[C]](s32)
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; MIPS32R2: [[AND7:%[0-9]+]]:_(s32) = G_AND [[SHL3]], [[C1]]
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; MIPS32R2: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[AND7]]
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||
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; MIPS32R2: [[AND8:%[0-9]+]]:_(s32) = G_AND [[OR3]], [[C3]]
|
||
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; MIPS32R2: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND8]], [[C2]](s32)
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||
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; MIPS32R2: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[OR3]], [[C2]](s32)
|
||
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; MIPS32R2: [[AND9:%[0-9]+]]:_(s32) = G_AND [[SHL4]], [[C3]]
|
||
|
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; MIPS32R2: [[OR4:%[0-9]+]]:_(s32) = G_OR [[LSHR4]], [[AND9]]
|
||
|
|
; MIPS32R2: [[AND10:%[0-9]+]]:_(s32) = G_AND [[OR4]], [[C5]]
|
||
|
|
; MIPS32R2: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[C4]](s32)
|
||
|
|
; MIPS32R2: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[OR4]], [[C4]](s32)
|
||
|
|
; MIPS32R2: [[AND11:%[0-9]+]]:_(s32) = G_AND [[SHL5]], [[C5]]
|
||
|
|
; MIPS32R2: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR5]], [[AND11]]
|
||
|
|
; MIPS32R2: $v0 = COPY [[OR2]](s32)
|
||
|
|
; MIPS32R2: $v1 = COPY [[OR5]](s32)
|
||
|
|
; MIPS32R2: RetRA implicit $v0, implicit $v1
|
||
|
|
%1:_(s32) = COPY $a0
|
||
|
|
%2:_(s32) = COPY $a1
|
||
|
|
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
|
||
|
|
%3:_(s64) = G_BITREVERSE %0
|
||
|
|
%4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64)
|
||
|
|
$v0 = COPY %4(s32)
|
||
|
|
$v1 = COPY %5(s32)
|
||
|
|
RetRA implicit $v0, implicit $v1
|
||
|
|
|
||
|
|
...
|