131 lines
4.6 KiB
Plaintext
131 lines
4.6 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
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--- |
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define void @mul_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
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define void @mul_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
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define void @mul_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
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define void @mul_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
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...
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---
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name: mul_v16i8
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1, $a2
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; P5600-LABEL: name: mul_v16i8
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; P5600: liveins: $a0, $a1, $a2
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; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
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; P5600: [[LD_B:%[0-9]+]]:msa128b = LD_B [[COPY]], 0 :: (load 16 from %ir.a)
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; P5600: [[LD_B1:%[0-9]+]]:msa128b = LD_B [[COPY1]], 0 :: (load 16 from %ir.b)
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; P5600: [[MULV_B:%[0-9]+]]:msa128b = MULV_B [[LD_B1]], [[LD_B]]
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; P5600: ST_B [[MULV_B]], [[COPY2]], 0 :: (store 16 into %ir.c)
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; P5600: RetRA
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%0:gprb(p0) = COPY $a0
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%1:gprb(p0) = COPY $a1
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%2:gprb(p0) = COPY $a2
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%3:fprb(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
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%4:fprb(<16 x s8>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
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%5:fprb(<16 x s8>) = G_MUL %4, %3
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G_STORE %5(<16 x s8>), %2(p0) :: (store 16 into %ir.c)
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RetRA
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...
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---
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name: mul_v8i16
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1, $a2
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; P5600-LABEL: name: mul_v8i16
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; P5600: liveins: $a0, $a1, $a2
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; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
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; P5600: [[LD_H:%[0-9]+]]:msa128h = LD_H [[COPY]], 0 :: (load 16 from %ir.a)
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; P5600: [[LD_H1:%[0-9]+]]:msa128h = LD_H [[COPY1]], 0 :: (load 16 from %ir.b)
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; P5600: [[MULV_H:%[0-9]+]]:msa128h = MULV_H [[LD_H1]], [[LD_H]]
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; P5600: ST_H [[MULV_H]], [[COPY2]], 0 :: (store 16 into %ir.c)
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; P5600: RetRA
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%0:gprb(p0) = COPY $a0
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%1:gprb(p0) = COPY $a1
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%2:gprb(p0) = COPY $a2
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%3:fprb(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
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%4:fprb(<8 x s16>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
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%5:fprb(<8 x s16>) = G_MUL %4, %3
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G_STORE %5(<8 x s16>), %2(p0) :: (store 16 into %ir.c)
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RetRA
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...
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---
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name: mul_v4i32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1, $a2
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; P5600-LABEL: name: mul_v4i32
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; P5600: liveins: $a0, $a1, $a2
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; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
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; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load 16 from %ir.a)
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; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load 16 from %ir.b)
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; P5600: [[MULV_W:%[0-9]+]]:msa128w = MULV_W [[LD_W1]], [[LD_W]]
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; P5600: ST_W [[MULV_W]], [[COPY2]], 0 :: (store 16 into %ir.c)
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; P5600: RetRA
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%0:gprb(p0) = COPY $a0
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%1:gprb(p0) = COPY $a1
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%2:gprb(p0) = COPY $a2
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%3:fprb(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
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%4:fprb(<4 x s32>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
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%5:fprb(<4 x s32>) = G_MUL %4, %3
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G_STORE %5(<4 x s32>), %2(p0) :: (store 16 into %ir.c)
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RetRA
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...
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---
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name: mul_v2i64
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1, $a2
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; P5600-LABEL: name: mul_v2i64
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; P5600: liveins: $a0, $a1, $a2
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; P5600: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; P5600: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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; P5600: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
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; P5600: [[LD_D:%[0-9]+]]:msa128d = LD_D [[COPY]], 0 :: (load 16 from %ir.a)
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; P5600: [[LD_D1:%[0-9]+]]:msa128d = LD_D [[COPY1]], 0 :: (load 16 from %ir.b)
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; P5600: [[MULV_D:%[0-9]+]]:msa128d = MULV_D [[LD_D1]], [[LD_D]]
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; P5600: ST_D [[MULV_D]], [[COPY2]], 0 :: (store 16 into %ir.c)
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; P5600: RetRA
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%0:gprb(p0) = COPY $a0
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%1:gprb(p0) = COPY $a1
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%2:gprb(p0) = COPY $a2
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%3:fprb(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.a)
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%4:fprb(<2 x s64>) = G_LOAD %1(p0) :: (load 16 from %ir.b)
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%5:fprb(<2 x s64>) = G_MUL %4, %3
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G_STORE %5(<2 x s64>), %2(p0) :: (store 16 into %ir.c)
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RetRA
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...
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