llvm-for-llvmta/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-cl...

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2022-04-25 10:02:23 +02:00
# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
---
name: wrong_reg_class_scratch_rsrc_reg
machineFunctionInfo:
scratchRSrcReg: '$vgpr0_vgpr1_vgpr2_vgpr3'
# CHECK: :[[@LINE-1]]:{{[0-9]+}}: incorrect register class for field
body: |
bb.0:
S_ENDPGM
...