73 lines
2.1 KiB
LLVM
73 lines
2.1 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=hexagon -hexagon-instsimplify=0 < %s | FileCheck %s
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; Check that this compiles successfully.
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target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
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target triple = "hexagon"
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define i32 @fred(<8 x i16>* %a0) #0 {
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; CHECK-LABEL: fred:
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; CHECK: // %bb.0: // %b0
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; CHECK-NEXT: {
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; CHECK-NEXT: if (p0) jump:nt .LBB0_2
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; CHECK-NEXT: }
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; CHECK-NEXT: // %bb.1: // %b2
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; CHECK-NEXT: {
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; CHECK-NEXT: r3:2 = combine(#0,#0)
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; CHECK-NEXT: r1:0 = memd(r0+#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: p0 = vcmph.eq(r1:0,r3:2)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r1:0 = mask(p0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = and(r0,#1)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: p0 = cmp.eq(r0,#11)
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; CHECK-NEXT: r0 = #1
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: if (p0) r0 = #0
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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; CHECK-NEXT: .LBB0_2: // %b14
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; CHECK-NEXT: {
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; CHECK-NEXT: r0 = #0
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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b0:
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switch i32 undef, label %b14 [
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i32 5, label %b2
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i32 3, label %b1
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]
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b1: ; preds = %b0
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br label %b14
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b2: ; preds = %b0
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%v2 = load <8 x i16>, <8 x i16>* %a0, align 64
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%v3 = icmp eq <8 x i16> %v2, zeroinitializer
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%v4 = zext <8 x i1> %v3 to <8 x i16>
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%v5 = add <8 x i16> zeroinitializer, %v4
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%v6 = add <8 x i16> %v5, zeroinitializer
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%v7 = add <8 x i16> %v6, zeroinitializer
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%v8 = extractelement <8 x i16> %v7, i32 0
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%v9 = add i16 %v8, 0
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%v10 = add i16 %v9, 0
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%v11 = add i16 %v10, 0
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%v12 = icmp eq i16 %v11, 11
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br i1 %v12, label %b14, label %b13
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b13: ; preds = %b2
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ret i32 1
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b14: ; preds = %b2, %b1, %b0
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ret i32 0
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" }
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