llvm-for-llvmta/test/CodeGen/Hexagon/vect/vect-vsubw.ll

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2022-04-25 10:02:23 +02:00
; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK: vsubw
define <2 x i32> @t_i2x32(<2 x i32> %a, <2 x i32> %b) nounwind {
entry:
%0 = sub <2 x i32> %a, %b
ret <2 x i32> %0
}