100 lines
3.8 KiB
LLVM
100 lines
3.8 KiB
LLVM
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; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
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; CHECK: v{{[0-9]+}}:{{[0-9]+}} = vcombine(v{{[0-9]+}},v{{[0-9]+}})
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target triple = "hexagon"
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; Function Attrs: nounwind
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define void @f0(i8* nocapture readnone %a0, i32 %a1, i32 %a2, i32 %a3, i32* nocapture %a4, i32 %a5) #0 {
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b0:
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%v0 = bitcast i32* %a4 to <16 x i32>*
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%v1 = mul i32 %a5, -2
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%v2 = add i32 %v1, %a1
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%v3 = and i32 %a5, 63
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%v4 = add i32 %v2, %v3
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%v5 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 -1)
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%v6 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1)
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%v7 = tail call <64 x i1> @llvm.hexagon.V6.pred.scalar2(i32 %v4)
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%v8 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt.acc(<16 x i32> %v6, <64 x i1> %v7, i32 12)
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%v9 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v8, <16 x i32> %v8)
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%v10 = and i32 %v4, 511
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%v11 = icmp eq i32 %v10, 0
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br i1 %v11, label %b1, label %b2
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b1: ; preds = %b0
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%v12 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v5, <16 x i32> %v8)
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br label %b2
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b2: ; preds = %b1, %b0
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%v13 = phi <32 x i32> [ %v12, %b1 ], [ %v9, %b0 ]
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%v14 = icmp sgt i32 %v4, 0
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br i1 %v14, label %b3, label %b6
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b3: ; preds = %b2
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%v15 = tail call <64 x i1> @llvm.hexagon.V6.pred.scalar2(i32 %a5)
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%v16 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %v15, i32 16843009)
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%v17 = tail call <16 x i32> @llvm.hexagon.V6.vnot(<16 x i32> %v16)
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%v18 = add i32 %v3, %a1
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%v19 = add i32 %v18, -1
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%v20 = add i32 %v19, %v1
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%v21 = lshr i32 %v20, 9
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%v22 = mul i32 %v21, 16
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%v23 = add nuw nsw i32 %v22, 16
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%v24 = getelementptr i32, i32* %a4, i32 %v23
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br label %b4
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b4: ; preds = %b4, %b3
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%v25 = phi i32 [ %v4, %b3 ], [ %v30, %b4 ]
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%v26 = phi <16 x i32> [ %v17, %b3 ], [ %v5, %b4 ]
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%v27 = phi <16 x i32>* [ %v0, %b3 ], [ %v29, %b4 ]
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%v28 = tail call <16 x i32> @llvm.hexagon.V6.vand(<16 x i32> undef, <16 x i32> %v26)
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%v29 = getelementptr inbounds <16 x i32>, <16 x i32>* %v27, i32 1
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store <16 x i32> %v28, <16 x i32>* %v27, align 64, !tbaa !0
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%v30 = add nsw i32 %v25, -512
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%v31 = icmp sgt i32 %v30, 0
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br i1 %v31, label %b4, label %b5
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b5: ; preds = %b4
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%v32 = bitcast i32* %v24 to <16 x i32>*
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br label %b6
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b6: ; preds = %b5, %b2
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%v33 = phi <16 x i32>* [ %v32, %b5 ], [ %v0, %b2 ]
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%v34 = load <16 x i32>, <16 x i32>* %v33, align 64, !tbaa !0
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%v35 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v13)
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%v36 = tail call <16 x i32> @llvm.hexagon.V6.vand(<16 x i32> %v34, <16 x i32> %v35)
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store <16 x i32> %v36, <16 x i32>* %v33, align 64, !tbaa !0
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ret void
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}
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
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; Function Attrs: nounwind readnone
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declare <64 x i1> @llvm.hexagon.V6.pred.scalar2(i32) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vandqrt.acc(<16 x i32>, <64 x i1>, i32) #1
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vnot(<16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vand(<16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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attributes #1 = { nounwind readnone }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"omnipotent char", !2, i64 0}
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!2 = !{!"Simple C/C++ TBAA"}
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