63 lines
3.3 KiB
LLVM
63 lines
3.3 KiB
LLVM
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; Test that we generate a .cur
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; CHECK: v{{[0-9]*}}.cur
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; Function Attrs: nounwind
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define void @f0(i8* noalias nocapture readonly %a0, i32 %a1, i32 %a2, <16 x i32>* %a3, <16 x i32>* %a4) #0 {
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b0:
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br i1 undef, label %b1, label %b3
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b1: ; preds = %b0
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br label %b2
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b2: ; preds = %b2, %b1
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%v0 = phi i8* [ %a0, %b1 ], [ %v4, %b2 ]
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%v1 = phi i32 [ 0, %b1 ], [ %v23, %b2 ]
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%v2 = phi <16 x i32> [ zeroinitializer, %b1 ], [ %v6, %b2 ]
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%v3 = phi <16 x i32> [ zeroinitializer, %b1 ], [ zeroinitializer, %b2 ]
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%v4 = getelementptr inbounds i8, i8* %v0, i32 64
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%v5 = bitcast i8* %v4 to <16 x i32>*
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%v6 = load <16 x i32>, <16 x i32>* %v5, align 64, !tbaa !0
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%v7 = load <16 x i32>, <16 x i32>* %a3, align 64, !tbaa !0
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%v8 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v6, <16 x i32> %v2, i32 4)
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%v9 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> zeroinitializer, <16 x i32> %v3, i32 4)
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%v10 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v7, <16 x i32> zeroinitializer, i32 4)
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%v11 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v8, <16 x i32> %v2)
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%v12 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v10, <16 x i32> zeroinitializer)
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%v13 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32> %v11, i32 0, i32 0)
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%v14 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v13, <32 x i32> zeroinitializer, i32 undef, i32 0)
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%v15 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v14, <32 x i32> undef, i32 undef, i32 0)
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%v16 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v15)
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%v17 = tail call <16 x i32> @llvm.hexagon.V6.vasrwh(<16 x i32> %v16, <16 x i32> undef, i32 %a1)
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%v18 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> undef, <16 x i32> %v17)
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store <16 x i32> %v18, <16 x i32>* %a3, align 64, !tbaa !0
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%v19 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> zeroinitializer, <32 x i32> %v12, i32 undef, i32 1)
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%v20 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v19)
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%v21 = tail call <16 x i32> @llvm.hexagon.V6.vasrwh(<16 x i32> %v20, <16 x i32> undef, i32 %a1)
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%v22 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> %v21, <16 x i32> undef)
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store <16 x i32> %v22, <16 x i32>* %a4, align 64, !tbaa !0
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%v23 = add nsw i32 %v1, 64
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%v24 = icmp slt i32 %v23, %a2
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br i1 %v24, label %b2, label %b3
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b3: ; preds = %b2, %b0
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ret void
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}
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declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #1
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declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #1
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declare <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32>, i32, i32) #1
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declare <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32>, <32 x i32>, i32, i32) #1
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declare <16 x i32> @llvm.hexagon.V6.vasrwh(<16 x i32>, <16 x i32>, i32) #1
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declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
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declare <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32>, <16 x i32>) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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attributes #1 = { nounwind readnone }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"omnipotent char", !2, i64 0}
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!2 = !{!"Simple C/C++ TBAA"}
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