45 lines
1.7 KiB
LLVM
45 lines
1.7 KiB
LLVM
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; RUN: llc -march=hexagon -hexagon-bit=false < %s
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; REQUIRES: asserts
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; Fix for an undefined virtual register assert that was caused by an
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; incorrect phi generated by the pipeliner. In this case, there is a
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; phi that defines a value used by another phi in the next iteration.
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; The pipeliner code for generating new phis was assuming that the
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; definition is processed before the use, so an incorrect value was
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; used.
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; Function Attrs: nounwind
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define void @f0() local_unnamed_addr #0 {
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b0:
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br label %b1
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b1: ; preds = %b1, %b0
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%v0 = phi i64 [ 0, %b0 ], [ %v5, %b1 ]
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%v1 = phi i64 [ undef, %b0 ], [ %v9, %b1 ]
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%v2 = phi i32 [ 0, %b0 ], [ %v10, %b1 ]
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%v3 = phi i32 [ undef, %b0 ], [ %v4, %b1 ]
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%v4 = phi i32 [ undef, %b0 ], [ %v8, %b1 ]
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%v5 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 %v0, i64 %v1, i64 undef)
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%v6 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v3, i32 %v3)
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%v7 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 undef, i64 %v6, i64 undef)
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%v8 = tail call i32 @llvm.hexagon.A2.combine.ll(i32 undef, i32 undef)
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%v9 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v8, i32 %v4)
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%v10 = add nuw nsw i32 %v2, 1
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%v11 = icmp eq i32 %v10, undef
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br i1 %v11, label %b2, label %b1
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b2: ; preds = %b1
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%v12 = lshr i64 %v7, 32
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%v13 = trunc i64 %v12 to i32
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store i32 %v13, i32* undef, align 4
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%v14 = lshr i64 %v5, 32
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ret void
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}
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declare i32 @llvm.hexagon.A2.combine.ll(i32, i32) #1
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declare i64 @llvm.hexagon.A2.combinew(i32, i32) #1
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declare i64 @llvm.hexagon.M2.vdmacs.s0(i64, i64, i64) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv65" }
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attributes #1 = { nounwind readnone }
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