170 lines
7.4 KiB
LLVM
170 lines
7.4 KiB
LLVM
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; RUN: llc -march=hexagon -O2 -simplifycfg-require-and-preserve-domtree=1 < %s
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; REQUIRES: asserts
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; Test that we generate the correct Phi names in the epilog when we need
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; to reuse an existing Phi. This bug caused an assert in live variable
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; analysis because the wrong virtual register was used.
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; The bug occurs when a Phi references another Phi, and referent Phi
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; value is used in multiple stages. When this occurs, the referring Phi
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; can reuse one of the new values. We have code that deals with this in the
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; kernel, but this case can occur in the epilog too.
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #0
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32>, <32 x i32>, i32) #0
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32>, <16 x i32>, i32) #0
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #0
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #0
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #0
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #0
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vmpyiwb.acc(<16 x i32>, <16 x i32>, i32) #0
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vshuffob(<16 x i32>, <16 x i32>) #0
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; Function Attrs: nounwind
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define void @f0(i8* noalias nocapture readonly %a0, i32 %a1, i32 %a2) #1 {
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b0:
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%v0 = mul nsw i32 %a1, 2
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br i1 undef, label %b1, label %b5
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b1: ; preds = %b0
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%v1 = getelementptr inbounds i8, i8* %a0, i32 %v0
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%v2 = icmp sgt i32 %a2, 64
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%v3 = add i32 %v0, 64
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%v4 = add i32 %a1, 64
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%v5 = sub i32 64, %a1
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%v6 = sub i32 64, %v0
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br i1 %v2, label %b2, label %b4
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b2: ; preds = %b1
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%v7 = getelementptr inbounds i8, i8* %v1, i32 %v3
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%v8 = getelementptr inbounds i8, i8* %v1, i32 %v4
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%v9 = getelementptr inbounds i8, i8* %v1, i32 64
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%v10 = getelementptr inbounds i8, i8* %v1, i32 %v5
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%v11 = getelementptr inbounds i8, i8* %v1, i32 %v6
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%v12 = bitcast i8* %v7 to <16 x i32>*
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%v13 = bitcast i8* %v8 to <16 x i32>*
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%v14 = bitcast i8* %v9 to <16 x i32>*
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%v15 = bitcast i8* %v10 to <16 x i32>*
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%v16 = bitcast i8* %v11 to <16 x i32>*
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br label %b3
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b3: ; preds = %b3, %b2
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%v17 = phi <16 x i32>* [ null, %b2 ], [ %v52, %b3 ]
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%v18 = phi <16 x i32>* [ %v12, %b2 ], [ %v34, %b3 ]
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%v19 = phi <16 x i32>* [ %v13, %b2 ], [ %v32, %b3 ]
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%v20 = phi <16 x i32>* [ %v14, %b2 ], [ %v30, %b3 ]
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%v21 = phi <16 x i32>* [ %v15, %b2 ], [ %v28, %b3 ]
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%v22 = phi <16 x i32>* [ %v16, %b2 ], [ %v26, %b3 ]
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%v23 = phi <32 x i32> [ undef, %b2 ], [ %v37, %b3 ]
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%v24 = phi <32 x i32> [ zeroinitializer, %b2 ], [ %v23, %b3 ]
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%v25 = phi i32 [ %a2, %b2 ], [ %v53, %b3 ]
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%v26 = getelementptr inbounds <16 x i32>, <16 x i32>* %v22, i32 1
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%v27 = load <16 x i32>, <16 x i32>* %v22, align 64
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%v28 = getelementptr inbounds <16 x i32>, <16 x i32>* %v21, i32 1
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%v29 = load <16 x i32>, <16 x i32>* %v21, align 64
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%v30 = getelementptr inbounds <16 x i32>, <16 x i32>* %v20, i32 1
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%v31 = load <16 x i32>, <16 x i32>* %v20, align 64
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%v32 = getelementptr inbounds <16 x i32>, <16 x i32>* %v19, i32 1
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%v33 = load <16 x i32>, <16 x i32>* %v19, align 64
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%v34 = getelementptr inbounds <16 x i32>, <16 x i32>* %v18, i32 1
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%v35 = load <16 x i32>, <16 x i32>* %v18, align 64
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%v36 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v33, <16 x i32> %v29) #3
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%v37 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> undef, <32 x i32> %v36, i32 67372036) #3
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%v38 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v23) #3
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%v39 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v24) #3
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%v40 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v38, <16 x i32> %v39, i32 2) #3
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%v41 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v37) #3
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%v42 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v41, <16 x i32> %v38, i32 2) #3
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%v43 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v37) #3
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%v44 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v43, <16 x i32> undef, i32 2) #3
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%v45 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v40, <16 x i32> %v42) #3
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%v46 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiwb.acc(<16 x i32> %v45, <16 x i32> %v38, i32 101058054) #3
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%v47 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiwb.acc(<16 x i32> %v46, <16 x i32> zeroinitializer, i32 67372036) #3
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%v48 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> undef, <16 x i32> %v44) #3
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%v49 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiwb.acc(<16 x i32> %v48, <16 x i32> undef, i32 101058054) #3
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%v50 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiwb.acc(<16 x i32> %v49, <16 x i32> zeroinitializer, i32 67372036) #3
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%v51 = tail call <16 x i32> @llvm.hexagon.V6.vshuffob(<16 x i32> %v50, <16 x i32> %v47) #3
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%v52 = getelementptr inbounds <16 x i32>, <16 x i32>* %v17, i32 1
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store <16 x i32> %v51, <16 x i32>* %v17, align 64
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%v53 = add nsw i32 %v25, -64
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%v54 = icmp sgt i32 %v53, 64
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br i1 %v54, label %b3, label %b4
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b4: ; preds = %b3, %b1
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unreachable
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b5: ; preds = %b0
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ret void
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}
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; Function Attrs: nounwind
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define void @f1(i32 %a0, i32* %a1) #1 {
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b0:
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%v0 = ptrtoint i32* %a1 to i32
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%v1 = ashr i32 %a0, 1
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%v2 = tail call i32 @llvm.hexagon.A2.combine.ll(i32 undef, i32 undef)
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br i1 undef, label %b1, label %b2
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b1: ; preds = %b1, %b0
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br i1 undef, label %b1, label %b2
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b2: ; preds = %b2, %b1, %b0
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%v3 = phi i64 [ %v11, %b2 ], [ undef, %b0 ], [ undef, %b1 ]
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%v4 = phi i32 [ %v12, %b2 ], [ 0, %b0 ], [ undef, %b1 ]
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%v5 = phi i32 [ %v6, %b2 ], [ %v2, %b0 ], [ undef, %b1 ]
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%v6 = phi i32 [ %v10, %b2 ], [ undef, %b0 ], [ undef, %b1 ]
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%v7 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 undef, i64 %v3, i64 undef)
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%v8 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v5, i32 %v5)
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%v9 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 undef, i64 %v8, i64 undef)
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%v10 = tail call i32 @llvm.hexagon.A2.combine.ll(i32 0, i32 undef)
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%v11 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v10, i32 %v6)
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%v12 = add nsw i32 %v4, 1
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%v13 = icmp eq i32 %v12, %v1
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br i1 %v13, label %b3, label %b2
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b3: ; preds = %b2
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%v14 = phi i64 [ %v9, %b2 ]
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%v15 = phi i64 [ %v7, %b2 ]
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%v16 = trunc i64 %v14 to i32
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%v17 = trunc i64 %v15 to i32
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%v18 = inttoptr i32 %v0 to i32*
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store i32 %v17, i32* %v18, align 4
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%v19 = bitcast i8* undef to i32*
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store i32 %v16, i32* %v19, align 4
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call void @llvm.trap()
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unreachable
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.A2.combine.ll(i32, i32) #0
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; Function Attrs: nounwind readnone
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declare i64 @llvm.hexagon.A2.combinew(i32, i32) #0
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; Function Attrs: nounwind readnone
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declare i64 @llvm.hexagon.M2.vdmacs.s0(i64, i64, i64) #0
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; Function Attrs: noreturn nounwind
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declare void @llvm.trap() #2
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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attributes #2 = { noreturn nounwind }
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attributes #3 = { nounwind }
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