60 lines
2.3 KiB
LLVM
60 lines
2.3 KiB
LLVM
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; Test that the store widening optimization correctly transforms to a wider
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; instruction with a sub register. Recently, the store widening occurs in the
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; DAG combiner, so this test doesn't fail any more.
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; CHECK: memh({{r[0-9]+}}+#{{[0-9]+}}) =
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%s.0 = type { %s.1, %s.2, %s.3*, %s.0*, i32, i8, i8, i32, i8, i8, i32, i32, i8, i32, %s.4*, [2 x %s.4*], %s.13, i8*, %s.15*, %s.26, i32, i32, i32 }
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%s.1 = type { i64, [8 x i8] }
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%s.2 = type { i64*, i32, i8 }
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%s.3 = type { %s.1, %s.26, %s.26, i32, i32, i32, void (%s.1*)*, void (%s.1*)*, i32 (%s.1*)*, void (%s.1*)*, i32, i64* }
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%s.4 = type { %s.5, %s.12 }
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%s.5 = type { i32, i32, i32, i32, i32, i32, i32, i32, %s.6 }
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%s.6 = type { %s.7 }
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%s.7 = type { i32, i32, %s.8, %s.9, i32, [4 x %s.10], %s.11 }
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%s.8 = type { i32, i32, i32 }
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%s.9 = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
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%s.10 = type { i32, i32 }
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%s.11 = type { i32, i32, i32, i32, i32, i32, i32, i32 }
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%s.12 = type { i32, i32, i32, i32, i32, i32, i32 }
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%s.13 = type { i32, i32, i32, %s.14*, %s.14*, %s.14*, %s.14*, i32 }
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%s.14 = type { %s.14*, i8, i32, %s.4*, i32, %s.4* }
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%s.15 = type { %s.16, %s.17, %s.19, %s.20, %s.21, %s.24 }
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%s.16 = type { i64, i64, i64, i32 }
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%s.17 = type { i16, i16, i8, [4 x %s.18], i8, i8 }
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%s.18 = type { i32, i32 }
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%s.19 = type { i32*, i32, i32* }
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%s.20 = type { i8, i8, i32, i32, i8, i32, i32, i32, i32, i32 }
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%s.21 = type { i32, %s.22 }
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%s.22 = type { %s.23 }
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%s.23 = type { i32, i32, i32, i32, i32, i32, i32 }
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%s.24 = type { %s.25 }
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%s.25 = type { i32, i32, i32, i32, i32, i32, i32 }
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%s.26 = type { %s.27 }
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%s.27 = type { i16, i16, i32, i32, i32 }
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; Function Attrs: nounwind
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define void @f0(i64* %a0, i1 %a1) #0 {
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b0:
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%v0 = load i64, i64* %a0, align 8
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br i1 %a1, label %b1, label %b2
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b1: ; preds = %b0
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%v1 = trunc i64 %v0 to i32
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%v2 = inttoptr i32 %v1 to %s.0*
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%v3 = getelementptr inbounds %s.0, %s.0* %v2, i32 0, i32 8
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store i8 0, i8* %v3, align 8
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%v4 = getelementptr inbounds %s.0, %s.0* %v2, i32 0, i32 9
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store i8 1, i8* %v4, align 1
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%v5 = getelementptr inbounds %s.0, %s.0* %v2, i32 0, i32 6
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store i8 1, i8* %v5, align 1
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ret void
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b2: ; preds = %b0
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ret void
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}
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attributes #0 = { nounwind }
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