135 lines
7.6 KiB
Plaintext
135 lines
7.6 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
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# XUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
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---
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name: buffer_load_ss
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4
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; CHECK-LABEL: name: buffer_load_ss
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; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4
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; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
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; CHECK: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<4 x s32>) = G_AMDGPU_S_BUFFER_LOAD [[COPY]](<4 x s32>), [[COPY1]](s32), 0
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%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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%1:_(s32) = COPY $sgpr4
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%2:_(<4 x s32>) = G_AMDGPU_S_BUFFER_LOAD %0, %1, 0
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...
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---
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name: buffer_load_sv
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $vgpr0
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; CHECK-LABEL: name: buffer_load_sv
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; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $vgpr0
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; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
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; CHECK: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
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; CHECK: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[COPY]](<4 x s32>), [[C1]](s32), [[COPY1]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)
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%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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%1:_(s32) = COPY $vgpr0
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%2:_(<4 x s32>) = G_AMDGPU_S_BUFFER_LOAD %0, %1, 0
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...
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---
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name: buffer_load_vs
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr0
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; CHECK-LABEL: name: buffer_load_vs
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr0
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; CHECK: [[COPY:%[0-9]+]]:vgpr(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
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; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
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; CHECK: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
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; CHECK: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
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; CHECK: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
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; CHECK: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
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; CHECK: .1:
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; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.0, %9, %bb.1
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; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV]].sub0(s64), implicit $exec
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; CHECK: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV]].sub1(s64), implicit $exec
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; CHECK: [[MV:%[0-9]+]]:sreg_64_xexec(s64) = G_MERGE_VALUES [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32)
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; CHECK: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[MV]](s64), [[UV]](s64), implicit $exec
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; CHECK: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV1]].sub0(s64), implicit $exec
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; CHECK: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV1]].sub1(s64), implicit $exec
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; CHECK: [[MV1:%[0-9]+]]:sreg_64_xexec(s64) = G_MERGE_VALUES [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32)
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; CHECK: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[MV1]](s64), [[UV1]](s64), implicit $exec
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; CHECK: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32)
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; CHECK: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY2]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)
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; CHECK: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
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; CHECK: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
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; CHECK: S_CBRANCH_EXECNZ %bb.1, implicit $exec
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; CHECK: .2:
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; CHECK: successors: %bb.3(0x80000000)
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; CHECK: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
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; CHECK: .3:
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%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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%1:_(s32) = COPY $sgpr0
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%2:_(<4 x s32>) = G_AMDGPU_S_BUFFER_LOAD %0, %1, 0
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...
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---
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name: buffer_load_vv
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
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; CHECK-LABEL: name: buffer_load_vv
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
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; CHECK: [[COPY:%[0-9]+]]:vgpr(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr4
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; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
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; CHECK: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
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; CHECK: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
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; CHECK: [[UV:%[0-9]+]]:vreg_64(s64), [[UV1:%[0-9]+]]:vreg_64(s64) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
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; CHECK: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
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; CHECK: .1:
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; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK: [[PHI:%[0-9]+]]:sreg_64_xexec = PHI [[DEF]], %bb.0, %8, %bb.1
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; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV]].sub0(s64), implicit $exec
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; CHECK: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV]].sub1(s64), implicit $exec
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; CHECK: [[MV:%[0-9]+]]:sreg_64_xexec(s64) = G_MERGE_VALUES [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32)
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; CHECK: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[MV]](s64), [[UV]](s64), implicit $exec
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; CHECK: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV1]].sub0(s64), implicit $exec
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; CHECK: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0(s32) = V_READFIRSTLANE_B32 [[UV1]].sub1(s64), implicit $exec
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; CHECK: [[MV1:%[0-9]+]]:sreg_64_xexec(s64) = G_MERGE_VALUES [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32)
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; CHECK: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[MV1]](s64), [[UV1]](s64), implicit $exec
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; CHECK: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[V_READFIRSTLANE_B32_2]](s32), [[V_READFIRSTLANE_B32_3]](s32)
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; CHECK: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C1]](s32), [[COPY1]], [[C]], 0, 0, 0 :: (dereferenceable invariant load 16, align 4)
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; CHECK: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
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; CHECK: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
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; CHECK: S_CBRANCH_EXECNZ %bb.1, implicit $exec
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; CHECK: .2:
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; CHECK: successors: %bb.3(0x80000000)
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; CHECK: $exec = S_MOV_B64_term [[S_MOV_B64_term]]
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; CHECK: .3:
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%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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%1:_(s32) = COPY $vgpr4
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%2:_(<4 x s32>) = G_AMDGPU_S_BUFFER_LOAD %0, %1, 0
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...
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