117 lines
5.1 KiB
LLVM
117 lines
5.1 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9-32BANK %s
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; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX8-32BANK %s
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; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx810 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX8-16BANK %s
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define amdgpu_ps float @interp_f16(float %i, i32 inreg %m0) #0 {
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; GFX9-32BANK-LABEL: interp_f16:
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; GFX9-32BANK: ; %bb.0:
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; GFX9-32BANK-NEXT: s_mov_b32 m0, s0
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; GFX9-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
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; GFX9-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y
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; GFX9-32BANK-NEXT: ; return to shader part epilog
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;
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; GFX8-32BANK-LABEL: interp_f16:
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; GFX8-32BANK: ; %bb.0:
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; GFX8-32BANK-NEXT: s_mov_b32 m0, s0
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; GFX8-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
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; GFX8-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y
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; GFX8-32BANK-NEXT: ; return to shader part epilog
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;
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; GFX8-16BANK-LABEL: interp_f16:
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; GFX8-16BANK: ; %bb.0:
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; GFX8-16BANK-NEXT: s_mov_b32 m0, s0
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; GFX8-16BANK-NEXT: v_interp_mov_f32_e32 v1, p0, attr2.y
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; GFX8-16BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
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; GFX8-16BANK-NEXT: v_interp_p1lv_f16 v0, v0, attr2.y, v1
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; GFX8-16BANK-NEXT: ; return to shader part epilog
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%res = call float @llvm.amdgcn.interp.p1.f16(float %i, i32 1, i32 2, i1 false, i32 %m0)
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ret float %res
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}
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define amdgpu_ps float @interp_f16_high(float %i, i32 inreg %m0) #0 {
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; GFX9-32BANK-LABEL: interp_f16_high:
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; GFX9-32BANK: ; %bb.0:
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; GFX9-32BANK-NEXT: s_mov_b32 m0, s0
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; GFX9-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
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; GFX9-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y high
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; GFX9-32BANK-NEXT: ; return to shader part epilog
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;
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; GFX8-32BANK-LABEL: interp_f16_high:
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; GFX8-32BANK: ; %bb.0:
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; GFX8-32BANK-NEXT: s_mov_b32 m0, s0
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; GFX8-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
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; GFX8-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y high
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; GFX8-32BANK-NEXT: ; return to shader part epilog
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;
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; GFX8-16BANK-LABEL: interp_f16_high:
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; GFX8-16BANK: ; %bb.0:
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; GFX8-16BANK-NEXT: s_mov_b32 m0, s0
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; GFX8-16BANK-NEXT: v_interp_mov_f32_e32 v1, p0, attr2.y
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; GFX8-16BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
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; GFX8-16BANK-NEXT: v_interp_p1lv_f16 v0, v0, attr2.y, v1 high
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; GFX8-16BANK-NEXT: ; return to shader part epilog
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%res = call float @llvm.amdgcn.interp.p1.f16(float %i, i32 1, i32 2, i1 true, i32 %m0)
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ret float %res
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}
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define amdgpu_ps float @interp_f16_0_0(float %i, i32 inreg %m0) #0 {
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; GFX9-32BANK-LABEL: interp_f16_0_0:
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; GFX9-32BANK: ; %bb.0:
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; GFX9-32BANK-NEXT: s_mov_b32 m0, s0
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; GFX9-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
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; GFX9-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr0.x
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; GFX9-32BANK-NEXT: ; return to shader part epilog
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;
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; GFX8-32BANK-LABEL: interp_f16_0_0:
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; GFX8-32BANK: ; %bb.0:
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; GFX8-32BANK-NEXT: s_mov_b32 m0, s0
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; GFX8-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
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; GFX8-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr0.x
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; GFX8-32BANK-NEXT: ; return to shader part epilog
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;
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; GFX8-16BANK-LABEL: interp_f16_0_0:
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; GFX8-16BANK: ; %bb.0:
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; GFX8-16BANK-NEXT: s_mov_b32 m0, s0
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; GFX8-16BANK-NEXT: v_interp_mov_f32_e32 v1, p0, attr0.x
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; GFX8-16BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
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; GFX8-16BANK-NEXT: v_interp_p1lv_f16 v0, v0, attr0.x, v1
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; GFX8-16BANK-NEXT: ; return to shader part epilog
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%res = call float @llvm.amdgcn.interp.p1.f16(float %i, i32 0, i32 0, i1 false, i32 %m0)
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ret float %res
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}
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; Copy needed to legalize %i
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define amdgpu_ps float @interp_f16_sgpr_i(float inreg %i,i32 inreg %m0) #0 {
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; GFX9-32BANK-LABEL: interp_f16_sgpr_i:
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; GFX9-32BANK: ; %bb.0:
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; GFX9-32BANK-NEXT: v_mov_b32_e32 v0, s0
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; GFX9-32BANK-NEXT: s_mov_b32 m0, s1
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; GFX9-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
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; GFX9-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y
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; GFX9-32BANK-NEXT: ; return to shader part epilog
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;
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; GFX8-32BANK-LABEL: interp_f16_sgpr_i:
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; GFX8-32BANK: ; %bb.0:
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; GFX8-32BANK-NEXT: v_mov_b32_e32 v0, s0
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; GFX8-32BANK-NEXT: s_mov_b32 m0, s1
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; GFX8-32BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
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; GFX8-32BANK-NEXT: v_interp_p1ll_f16 v0, v0, attr2.y
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; GFX8-32BANK-NEXT: ; return to shader part epilog
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;
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; GFX8-16BANK-LABEL: interp_f16_sgpr_i:
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; GFX8-16BANK: ; %bb.0:
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; GFX8-16BANK-NEXT: s_mov_b32 m0, s1
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; GFX8-16BANK-NEXT: v_mov_b32_e32 v0, s0
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; GFX8-16BANK-NEXT: v_interp_mov_f32_e32 v1, p0, attr2.y
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; GFX8-16BANK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3
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; GFX8-16BANK-NEXT: v_interp_p1lv_f16 v0, v0, attr2.y, v1
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; GFX8-16BANK-NEXT: ; return to shader part epilog
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%res = call float @llvm.amdgcn.interp.p1.f16(float %i, i32 1, i32 2, i1 false, i32 %m0)
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ret float %res
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}
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declare float @llvm.amdgcn.interp.p1.f16(float, i32 immarg, i32 immarg, i1 immarg, i32) #0
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attributes #0 = { nounwind readnone speculatable }
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