158 lines
4.0 KiB
Plaintext
158 lines
4.0 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
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---
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name: zext_sgpr_s1_to_sgpr_s32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: zext_sgpr_s1_to_sgpr_s32
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1, implicit-def $scc
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; GCN: $sgpr0 = COPY [[S_AND_B32_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s1) = G_TRUNC %0
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%2:sgpr(s32) = G_ZEXT %1
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$sgpr0 = COPY %2
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...
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---
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name: zext_sgpr_s1_to_sgpr_s64
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: zext_sgpr_s1_to_sgpr_s64
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
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; GCN: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 [[REG_SEQUENCE]], 65536, implicit-def $scc
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; GCN: $sgpr0_sgpr1 = COPY [[S_BFE_U64_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s1) = G_TRUNC %0
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%2:sgpr(s64) = G_ZEXT %1
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$sgpr0_sgpr1 = COPY %2
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...
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---
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name: zext_sgpr_s16_to_sgpr_s32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: zext_sgpr_s16_to_sgpr_s32
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[S_BFE_U32_:%[0-9]+]]:sreg_32 = S_BFE_U32 [[COPY]], 1048576, implicit-def $scc
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; GCN: $sgpr0 = COPY [[S_BFE_U32_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s16) = G_TRUNC %0
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%2:sgpr(s32) = G_ZEXT %1
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$sgpr0 = COPY %2
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...
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---
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name: zext_sgpr_s16_to_sgpr_s64
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: zext_sgpr_s16_to_sgpr_s64
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
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; GCN: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 [[REG_SEQUENCE]], 1048576, implicit-def $scc
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; GCN: $sgpr0_sgpr1 = COPY [[S_BFE_U64_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s16) = G_TRUNC %0
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%2:sgpr(s64) = G_ZEXT %1
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$sgpr0_sgpr1 = COPY %2
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...
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# ---
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# name: zext_vcc_s1_to_vgpr_s32
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# legalized: true
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# regBankSelected: true
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# body: |
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# bb.0:
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# liveins: $vgpr0
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# %0:vgpr(s32) = COPY $vgpr0
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# %1:vcc(s1) = G_ICMP intpred(eq), %0, %0
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# %2:vgpr(s32) = G_ZEXT %1
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# $vgpr0 = COPY %2
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# ...
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---
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name: zext_vgpr_s1_to_vgpr_s32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: zext_vgpr_s1_to_vgpr_s32
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
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; GCN: $vgpr0 = COPY [[V_AND_B32_e32_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s1) = G_TRUNC %0
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%2:vgpr(s32) = G_ZEXT %1
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$vgpr0 = COPY %2
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...
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---
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name: zext_vgpr_s16_to_vgpr_s32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: zext_vgpr_s16_to_vgpr_s32
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[V_BFE_U32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_U32_e64 [[COPY]], 0, 16, implicit $exec
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; GCN: $vgpr0 = COPY [[V_BFE_U32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s16) = G_TRUNC %0
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%2:vgpr(s32) = G_ZEXT %1
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$vgpr0 = COPY %2
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...
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---
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name: zext_sgpr_reg_class_s1_to_sgpr_s32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: zext_sgpr_reg_class_s1_to_sgpr_s32
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; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1, implicit-def $scc
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; GCN: $sgpr0 = COPY [[S_AND_B32_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sreg_32(s1) = G_TRUNC %0
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%2:sgpr(s32) = G_ZEXT %1
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$sgpr0 = COPY %2
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...
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