601 lines
21 KiB
Plaintext
601 lines
21 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: insert_s512_s32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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; CHECK-LABEL: name: insert_s512_s32
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; CHECK: [[DEF:%[0-9]+]]:sgpr_512 = IMPLICIT_DEF
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; CHECK: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[DEF]], [[DEF1]], %subreg.sub0
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; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG]], [[DEF1]], %subreg.sub1
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; CHECK: [[INSERT_SUBREG2:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG1]], [[DEF1]], %subreg.sub2
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; CHECK: [[INSERT_SUBREG3:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG2]], [[DEF1]], %subreg.sub3
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; CHECK: [[INSERT_SUBREG4:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG3]], [[DEF1]], %subreg.sub4
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; CHECK: [[INSERT_SUBREG5:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG4]], [[DEF1]], %subreg.sub5
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; CHECK: [[INSERT_SUBREG6:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG5]], [[DEF1]], %subreg.sub6
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; CHECK: [[INSERT_SUBREG7:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG6]], [[DEF1]], %subreg.sub7
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; CHECK: [[INSERT_SUBREG8:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG7]], [[DEF1]], %subreg.sub8
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; CHECK: [[INSERT_SUBREG9:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG8]], [[DEF1]], %subreg.sub9
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; CHECK: [[INSERT_SUBREG10:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG9]], [[DEF1]], %subreg.sub10
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; CHECK: [[INSERT_SUBREG11:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG10]], [[DEF1]], %subreg.sub11
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; CHECK: [[INSERT_SUBREG12:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG11]], [[DEF1]], %subreg.sub12
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; CHECK: [[INSERT_SUBREG13:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG12]], [[DEF1]], %subreg.sub13
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; CHECK: [[INSERT_SUBREG14:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG13]], [[DEF1]], %subreg.sub14
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; CHECK: [[INSERT_SUBREG15:%[0-9]+]]:sgpr_512 = INSERT_SUBREG [[INSERT_SUBREG14]], [[DEF1]], %subreg.sub15
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; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY [[INSERT_SUBREG15]]
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; CHECK: SI_RETURN_TO_EPILOG $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
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%0:sgpr(s512) = G_IMPLICIT_DEF
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%1:sgpr(s32) = G_IMPLICIT_DEF
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%2:sgpr(s512) = G_INSERT %0:sgpr, %1:sgpr(s32), 0
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%3:sgpr(s512) = G_INSERT %2:sgpr, %1:sgpr(s32), 32
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%4:sgpr(s512) = G_INSERT %3:sgpr, %1:sgpr(s32), 64
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%5:sgpr(s512) = G_INSERT %4:sgpr, %1:sgpr(s32), 96
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%6:sgpr(s512) = G_INSERT %5:sgpr, %1:sgpr(s32), 128
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%7:sgpr(s512) = G_INSERT %6:sgpr, %1:sgpr(s32), 160
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%8:sgpr(s512) = G_INSERT %7:sgpr, %1:sgpr(s32), 192
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%9:sgpr(s512) = G_INSERT %8:sgpr, %1:sgpr(s32), 224
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%10:sgpr(s512) = G_INSERT %9:sgpr, %1:sgpr(s32), 256
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%11:sgpr(s512) = G_INSERT %10:sgpr, %1:sgpr(s32), 288
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%12:sgpr(s512) = G_INSERT %11:sgpr, %1:sgpr(s32), 320
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%13:sgpr(s512) = G_INSERT %12:sgpr, %1:sgpr(s32), 352
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%14:sgpr(s512) = G_INSERT %13:sgpr, %1:sgpr(s32), 384
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%15:sgpr(s512) = G_INSERT %14:sgpr, %1:sgpr(s32), 416
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%16:sgpr(s512) = G_INSERT %15:sgpr, %1:sgpr(s32), 448
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%17:sgpr(s512) = G_INSERT %16:sgpr, %1:sgpr(s32), 480
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$sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY %17:sgpr(s512)
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SI_RETURN_TO_EPILOG $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
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---
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name: insert_v_s64_v_s32_0
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2
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%0:vgpr(s64) = COPY $vgpr0_vgpr1
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%1:vgpr(s32) = COPY $vgpr2
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%2:vgpr(s64) = G_INSERT %0, %1, 0
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S_ENDPGM 0, implicit %2
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...
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---
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name: insert_v_s64_v_s32_32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2
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; CHECK-LABEL: name: insert_v_s64_v_s32_32
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; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1
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; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
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%0:vgpr(s64) = COPY $vgpr0_vgpr1
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%1:vgpr(s32) = COPY $vgpr2
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%2:vgpr(s64) = G_INSERT %0, %1, 32
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S_ENDPGM 0, implicit %2
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...
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---
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name: insert_s_s64_s_s32_0
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $sgpr2
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; CHECK-LABEL: name: insert_s_s64_s_s32_0
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; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0
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; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%1:sgpr(s32) = COPY $sgpr2
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%2:sgpr(s64) = G_INSERT %0, %1, 0
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S_ENDPGM 0, implicit %2
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...
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---
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name: insert_s_s64_s_s32_32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $sgpr2
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; CHECK-LABEL: name: insert_s_s64_s_s32_32
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; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1
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; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%1:sgpr(s32) = COPY $sgpr2
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%2:sgpr(s64) = G_INSERT %0, %1, 32
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S_ENDPGM 0, implicit %2
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...
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---
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name: insert_s_s64_v_s32_32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $vgpr0
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; CHECK-LABEL: name: insert_s_s64_v_s32_32
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; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1
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; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%1:vgpr(s32) = COPY $vgpr2
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%2:vgpr(s64) = G_INSERT %0, %1, 32
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S_ENDPGM 0, implicit %2
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...
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---
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name: insert_v_s64_s_s32_32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $sgpr0
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; CHECK-LABEL: name: insert_v_s64_s_s32_32
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; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1
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; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
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%0:vgpr(s64) = COPY $vgpr0_vgpr1
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%1:sgpr(s32) = COPY $sgpr0
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%2:vgpr(s64) = G_INSERT %0, %1, 32
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S_ENDPGM 0, implicit %2
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...
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---
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name: insert_v_s96_v_s64_0
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4
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; CHECK-LABEL: name: insert_v_s96_v_s64_0
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; CHECK: [[COPY:%[0-9]+]]:vreg_96 = COPY $vgpr0_vgpr1_vgpr2
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; CHECK: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_96 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1
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; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
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%0:vgpr(s96) = COPY $vgpr0_vgpr1_vgpr2
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%1:vgpr(s64) = COPY $vgpr3_vgpr4
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%2:vgpr(s96) = G_INSERT %0, %1, 0
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S_ENDPGM 0, implicit %2
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...
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---
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name: insert_v_s96_v_s64_32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2, $vgpr3_vgpr4
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; CHECK-LABEL: name: insert_v_s96_v_s64_32
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; CHECK: [[COPY:%[0-9]+]]:vreg_96 = COPY $vgpr0_vgpr1_vgpr2
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; CHECK: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_96 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1_sub2
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; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
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%0:vgpr(s96) = COPY $vgpr0_vgpr1_vgpr2
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%1:vgpr(s64) = COPY $vgpr3_vgpr4
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%2:vgpr(s96) = G_INSERT %0, %1, 32
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S_ENDPGM 0, implicit %2
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...
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---
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name: insert_s_s96_s_s64_0
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2, $sgpr4_sgpr5
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; CHECK-LABEL: name: insert_s_s96_s_s64_0
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; CHECK: [[COPY:%[0-9]+]]:sgpr_96_with_sub0_sub1 = COPY $sgpr0_sgpr1_sgpr2
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; CHECK: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_96 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1
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; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
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%0:sgpr(s96) = COPY $sgpr0_sgpr1_sgpr2
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%1:sgpr(s64) = COPY $sgpr4_sgpr5
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%2:sgpr(s96) = G_INSERT %0, %1, 0
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S_ENDPGM 0, implicit %2
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...
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---
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name: insert_s_s96_s_s64_32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2, $sgpr4_sgpr5
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; CHECK-LABEL: name: insert_s_s96_s_s64_32
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; CHECK: [[COPY:%[0-9]+]]:sgpr_96_with_sub1_sub2 = COPY $sgpr0_sgpr1_sgpr2
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; CHECK: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_96 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1_sub2
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; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
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%0:sgpr(s96) = COPY $sgpr0_sgpr1_sgpr2
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%1:sgpr(s64) = COPY $sgpr4_sgpr5
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%2:sgpr(s96) = G_INSERT %0, %1, 32
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S_ENDPGM 0, implicit %2
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...
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---
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name: insert_s_s128_s_s64_0
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5
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; CHECK-LABEL: name: insert_s_s128_s_s64_0
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; CHECK: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; CHECK: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1
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; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
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%0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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%1:sgpr(s64) = COPY $sgpr4_sgpr5
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%2:sgpr(s128) = G_INSERT %0, %1, 0
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S_ENDPGM 0, implicit %2
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...
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# ---
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# name: insert_s_s128_s_s64_32
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# legalized: true
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# regBankSelected: true
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# body: |
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# bb.0:
|
||
|
|
# liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5
|
||
|
|
# %0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||
|
|
# %1:sgpr(s64) = COPY $sgpr4_sgpr5
|
||
|
|
# %2:sgpr(s128) = G_INSERT %0, %1, 32
|
||
|
|
# S_ENDPGM 0, implicit %2
|
||
|
|
# ...
|
||
|
|
|
||
|
|
---
|
||
|
|
|
||
|
|
name: insert_s_s128_s_s64_64
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5
|
||
|
|
; CHECK-LABEL: name: insert_s_s128_s_s64_64
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||
|
|
; CHECK: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
|
||
|
|
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub2_sub3
|
||
|
|
; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
|
||
|
|
%0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||
|
|
%1:sgpr(s64) = COPY $sgpr4_sgpr5
|
||
|
|
%2:sgpr(s128) = G_INSERT %0, %1, 64
|
||
|
|
S_ENDPGM 0, implicit %2
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
|
||
|
|
name: insert_s_v256_v_s64_96
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9
|
||
|
|
; CHECK-LABEL: name: insert_s_v256_v_s64_96
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
|
||
|
|
; CHECK: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr8_vgpr9
|
||
|
|
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub3_sub4
|
||
|
|
; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
|
||
|
|
%0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
|
||
|
|
%1:vgpr(s64) = COPY $vgpr8_vgpr9
|
||
|
|
%2:vgpr(s256) = G_INSERT %0, %1, 96
|
||
|
|
S_ENDPGM 0, implicit %2
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
|
||
|
|
name: insert_s_s256_s_s64_128
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9
|
||
|
|
; CHECK-LABEL: name: insert_s_s256_s_s64_128
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
|
||
|
|
; CHECK: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
|
||
|
|
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub4_sub5
|
||
|
|
; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
|
||
|
|
%0:sgpr(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
|
||
|
|
%1:sgpr(s64) = COPY $sgpr4_sgpr5
|
||
|
|
%2:sgpr(s256) = G_INSERT %0, %1, 128
|
||
|
|
S_ENDPGM 0, implicit %2
|
||
|
|
...
|
||
|
|
|
||
|
|
# ---
|
||
|
|
|
||
|
|
# name: insert_s_s256_s_s64_160
|
||
|
|
# legalized: true
|
||
|
|
# regBankSelected: true
|
||
|
|
|
||
|
|
# body: |
|
||
|
|
# bb.0:
|
||
|
|
# liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9
|
||
|
|
# %0:sgpr(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
|
||
|
|
# %1:sgpr(s64) = COPY $sgpr4_sgpr5
|
||
|
|
# %2:sgpr(s256) = G_INSERT %0, %1, 160
|
||
|
|
# S_ENDPGM 0, implicit %2
|
||
|
|
# ...
|
||
|
|
|
||
|
|
---
|
||
|
|
|
||
|
|
name: insert_s_s128_s_s96_0
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr6_sgpr7_sgpr8
|
||
|
|
; CHECK-LABEL: name: insert_s_s128_s_s96_0
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:sgpr_128_with_sub0_sub1_sub2 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||
|
|
; CHECK: [[COPY1:%[0-9]+]]:sgpr_96 = COPY $sgpr6_sgpr7_sgpr8
|
||
|
|
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1_sub2
|
||
|
|
; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
|
||
|
|
%0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||
|
|
%1:sgpr(s96) = COPY $sgpr6_sgpr7_sgpr8
|
||
|
|
%2:sgpr(s128) = G_INSERT %0, %1, 0
|
||
|
|
S_ENDPGM 0, implicit %2
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
|
||
|
|
name: insert_s_s128_s_s96_32
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr6_sgpr7_sgpr8
|
||
|
|
; CHECK-LABEL: name: insert_s_s128_s_s96_32
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:sgpr_128_with_sub1_sub2_sub3 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||
|
|
; CHECK: [[COPY1:%[0-9]+]]:sgpr_96 = COPY $sgpr6_sgpr7_sgpr8
|
||
|
|
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1_sub2_sub3
|
||
|
|
; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
|
||
|
|
%0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||
|
|
%1:sgpr(s96) = COPY $sgpr6_sgpr7_sgpr8
|
||
|
|
%2:sgpr(s128) = G_INSERT %0, %1, 32
|
||
|
|
S_ENDPGM 0, implicit %2
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
|
||
|
|
name: insert_s_s160_s_s96_0
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4, $sgpr6_sgpr7_sgpr8
|
||
|
|
; CHECK-LABEL: name: insert_s_s160_s_s96_0
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:sgpr_160_with_sub0_sub1_sub2 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
|
||
|
|
; CHECK: [[COPY1:%[0-9]+]]:sgpr_96 = COPY $sgpr6_sgpr7_sgpr8
|
||
|
|
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_160 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1_sub2
|
||
|
|
; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
|
||
|
|
%0:sgpr(s160) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
|
||
|
|
%1:sgpr(s96) = COPY $sgpr6_sgpr7_sgpr8
|
||
|
|
%2:sgpr(s160) = G_INSERT %0, %1, 0
|
||
|
|
S_ENDPGM 0, implicit %2
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
|
||
|
|
name: insert_s_s160_s_s96_32
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4, $sgpr6_sgpr7_sgpr8
|
||
|
|
; CHECK-LABEL: name: insert_s_s160_s_s96_32
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:sgpr_160_with_sub1_sub2_sub3 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
|
||
|
|
; CHECK: [[COPY1:%[0-9]+]]:sgpr_96 = COPY $sgpr6_sgpr7_sgpr8
|
||
|
|
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_160 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1_sub2_sub3
|
||
|
|
; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
|
||
|
|
%0:sgpr(s160) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
|
||
|
|
%1:sgpr(s96) = COPY $sgpr6_sgpr7_sgpr8
|
||
|
|
%2:sgpr(s160) = G_INSERT %0, %1, 32
|
||
|
|
S_ENDPGM 0, implicit %2
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
|
||
|
|
name: insert_s_s160_s_s96_64
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4, $sgpr6_sgpr7_sgpr8
|
||
|
|
; CHECK-LABEL: name: insert_s_s160_s_s96_64
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:sgpr_160_with_sub2_sub3_sub4 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
|
||
|
|
; CHECK: [[COPY1:%[0-9]+]]:sgpr_96 = COPY $sgpr6_sgpr7_sgpr8
|
||
|
|
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_160 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub2_sub3_sub4
|
||
|
|
; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
|
||
|
|
%0:sgpr(s160) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4
|
||
|
|
%1:sgpr(s96) = COPY $sgpr6_sgpr7_sgpr8
|
||
|
|
%2:sgpr(s160) = G_INSERT %0, %1, 64
|
||
|
|
S_ENDPGM 0, implicit %2
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
|
||
|
|
name: insert_s_s256_s_s128_0
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: insert_s_s256_s_s128_0
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:sgpr_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
|
||
|
|
; CHECK: [[COPY1:%[0-9]+]]:sgpr_128 = COPY $sgpr8_sgpr9_sgpr10_sgpr11
|
||
|
|
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1_sub2_sub3
|
||
|
|
; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
|
||
|
|
%0:sgpr(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
|
||
|
|
%1:sgpr(s128) = COPY $sgpr8_sgpr9_sgpr10_sgpr11
|
||
|
|
%2:sgpr(s256) = G_INSERT %0, %1, 0
|
||
|
|
S_ENDPGM 0, implicit %2
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
|
||
|
|
name: insert_v_s256_v_s128_32
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: insert_v_s256_v_s128_32
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
|
||
|
|
; CHECK: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr8_vgpr9_vgpr10_vgpr11
|
||
|
|
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1_sub2_sub3_sub4
|
||
|
|
; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
|
||
|
|
%0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
|
||
|
|
%1:vgpr(s128) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
|
||
|
|
%2:vgpr(s256) = G_INSERT %0, %1, 32
|
||
|
|
S_ENDPGM 0, implicit %2
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
|
||
|
|
name: insert_v_s256_v_s128_64
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: insert_v_s256_v_s128_64
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
|
||
|
|
; CHECK: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr8_vgpr9_vgpr10_vgpr11
|
||
|
|
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub2_sub3_sub4_sub5
|
||
|
|
; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
|
||
|
|
%0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
|
||
|
|
%1:vgpr(s128) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
|
||
|
|
%2:vgpr(s256) = G_INSERT %0, %1, 64
|
||
|
|
S_ENDPGM 0, implicit %2
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
|
||
|
|
name: insert_v_s256_v_s128_96
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: insert_v_s256_v_s128_96
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
|
||
|
|
; CHECK: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr8_vgpr9_vgpr10_vgpr11
|
||
|
|
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub3_sub4_sub5_sub6
|
||
|
|
; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
|
||
|
|
%0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
|
||
|
|
%1:vgpr(s128) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
|
||
|
|
%2:vgpr(s256) = G_INSERT %0, %1, 96
|
||
|
|
S_ENDPGM 0, implicit %2
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
|
||
|
|
name: insert_v_s256_v_s128_128
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8_vgpr9_vgpr10_vgpr11
|
||
|
|
|
||
|
|
; CHECK-LABEL: name: insert_v_s256_v_s128_128
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
|
||
|
|
; CHECK: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr8_vgpr9_vgpr10_vgpr11
|
||
|
|
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub4_sub5_sub6_sub7
|
||
|
|
; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
|
||
|
|
%0:vgpr(s256) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
|
||
|
|
%1:vgpr(s128) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
|
||
|
|
%2:vgpr(s256) = G_INSERT %0, %1, 128
|
||
|
|
S_ENDPGM 0, implicit %2
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: insert_sgpr_v2s16_to_v4s16_offset0
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $sgpr0_sgpr1, $sgpr2
|
||
|
|
; CHECK-LABEL: name: insert_sgpr_v2s16_to_v4s16_offset0
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
||
|
|
; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
|
||
|
|
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0
|
||
|
|
; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
|
||
|
|
%0:sgpr(<4 x s16>) = COPY $sgpr0_sgpr1
|
||
|
|
%1:sgpr(<2 x s16>) = COPY $sgpr2
|
||
|
|
%2:sgpr(<4 x s16>) = G_INSERT %0, %1, 0
|
||
|
|
S_ENDPGM 0, implicit %2
|
||
|
|
|
||
|
|
...
|
||
|
|
|
||
|
|
---
|
||
|
|
name: insert_sgpr_v2s16_to_v4s16_offset32
|
||
|
|
legalized: true
|
||
|
|
regBankSelected: true
|
||
|
|
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
liveins: $sgpr0_sgpr1, $sgpr2
|
||
|
|
; CHECK-LABEL: name: insert_sgpr_v2s16_to_v4s16_offset32
|
||
|
|
; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
||
|
|
; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
|
||
|
|
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1
|
||
|
|
; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
|
||
|
|
%0:sgpr(<4 x s16>) = COPY $sgpr0_sgpr1
|
||
|
|
%1:sgpr(<2 x s16>) = COPY $sgpr2
|
||
|
|
%2:sgpr(<4 x s16>) = G_INSERT %0, %1, 32
|
||
|
|
S_ENDPGM 0, implicit %2
|