96 lines
4.1 KiB
Plaintext
96 lines
4.1 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE32 %s
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# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE64 %s
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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' %s -o /dev/null 2>&1 | FileCheck -check-prefix=SI-ERR %s
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# SI-ERR-NOT: remark
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# SI-ERR: remark: <unknown>:0:0: cannot select: %3:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2:sgpr(s16), %1:vgpr(s32) (in function: class_s16_vcc_sv)
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# SI-ERR-NEXT: remark: <unknown>:0:0: cannot select: %3:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2:vgpr(s16), %1:sgpr(s32) (in function: class_s16_vcc_vs)
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# SI-ERR-NEXT: remark: <unknown>:0:0: cannot select: %3:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2:vgpr(s16), %1:vgpr(s32) (in function: class_s16_vcc_vv)
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# SI-ERR-NOT: remark
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---
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name: class_s16_vcc_sv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; WAVE32-LABEL: name: class_s16_vcc_sv
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; WAVE32: liveins: $sgpr0, $vgpr0
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; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE32: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
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; WAVE64-LABEL: name: class_s16_vcc_sv
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; WAVE64: liveins: $sgpr0, $vgpr0
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; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE64: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = COPY $vgpr0
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%2:sgpr(s16) = G_TRUNC %0
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%4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1
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S_ENDPGM 0, implicit %4
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...
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---
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name: class_s16_vcc_vs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; WAVE32-LABEL: name: class_s16_vcc_vs
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; WAVE32: liveins: $sgpr0, $vgpr0
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; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; WAVE32: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
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; WAVE64-LABEL: name: class_s16_vcc_vs
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; WAVE64: liveins: $sgpr0, $vgpr0
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; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; WAVE64: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr(s32) = COPY $sgpr0
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%2:vgpr(s16) = G_TRUNC %0
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%4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1
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S_ENDPGM 0, implicit %4
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...
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---
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name: class_s16_vcc_vv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; WAVE32-LABEL: name: class_s16_vcc_vv
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; WAVE32: liveins: $vgpr0, $vgpr1
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; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE32: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
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; WAVE64-LABEL: name: class_s16_vcc_vv
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; WAVE64: liveins: $vgpr0, $vgpr1
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; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE64: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s16) = G_TRUNC %0
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%4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1
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S_ENDPGM 0, implicit %4
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...
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