93 lines
3.4 KiB
Plaintext
93 lines
3.4 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64"
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@x = dso_local global i32 -32768, align 4
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define dso_local i32 @check_sext_not_lost(i32* %ptr) {
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entry:
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%ptr.addr = alloca i32*, align 8
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store i32* %ptr, i32** %ptr.addr, align 8
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%0 = load i32*, i32** %ptr.addr, align 8
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%1 = load i32, i32* @x, align 4
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%sub = sub nsw i32 %1, 32768
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%conv = trunc i32 %sub to i16
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%idxprom = sext i16 %conv to i64
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%arrayidx = getelementptr inbounds i32, i32* %0, i64 %idxprom
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%2 = load i32, i32* %arrayidx, align 4
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ret i32 %2
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}
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...
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---
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name: check_sext_not_lost
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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- { id: 4, class: gpr }
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- { id: 5, class: gpr }
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- { id: 6, class: gpr }
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- { id: 7, class: _ }
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- { id: 8, class: gpr }
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- { id: 9, class: _ }
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- { id: 10, class: gpr }
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- { id: 11, class: gpr }
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- { id: 12, class: _ }
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- { id: 13, class: gpr }
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- { id: 14, class: gpr }
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- { id: 15, class: gpr64 }
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- { id: 16, class: gpr }
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liveins:
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- { reg: '$x0' }
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frameInfo:
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maxAlignment: 8
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maxCallFrameSize: 0
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stack:
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- { id: 0, name: ptr.addr, size: 8, alignment: 8 }
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $x0
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; CHECK-LABEL: name: check_sext_not_lost
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: STRXui [[COPY]], %stack.0.ptr.addr, 0 :: (store 8 into %ir.ptr.addr)
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; CHECK: [[LDRXui:%[0-9]+]]:gpr64common = LDRXui %stack.0.ptr.addr, 0 :: (dereferenceable load 8 from %ir.ptr.addr)
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; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @x
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; CHECK: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @x :: (dereferenceable load 4 from @x)
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; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = nsw SUBSWri [[LDRWui]], 8, 12, implicit-def $nzcv
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; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[SUBSWri]], %subreg.sub_32
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; CHECK: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[INSERT_SUBREG]], 0, 15
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; CHECK: [[LDRWroX:%[0-9]+]]:gpr32 = LDRWroX [[LDRXui]], [[SBFMXri]], 0, 1 :: (load 4 from %ir.arrayidx)
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; CHECK: $w0 = COPY [[LDRWroX]]
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; CHECK: RET_ReallyLR implicit $w0
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%0:gpr(p0) = COPY $x0
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%1:gpr(p0) = G_FRAME_INDEX %stack.0.ptr.addr
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G_STORE %0(p0), %1(p0) :: (store 8 into %ir.ptr.addr)
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%2:gpr(p0) = G_LOAD %1(p0) :: (dereferenceable load 8 from %ir.ptr.addr)
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%15:gpr64(p0) = ADRP target-flags(aarch64-page) @x
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%4:gpr(p0) = G_ADD_LOW %15(p0), target-flags(aarch64-pageoff, aarch64-nc) @x
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%3:gpr(s32) = G_LOAD %4(p0) :: (dereferenceable load 4 from @x)
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%5:gpr(s32) = G_CONSTANT i32 32768
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%6:gpr(s32) = nsw G_SUB %3, %5
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%16:gpr(s64) = G_ANYEXT %6(s32)
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%8:gpr(s64) = G_SEXT_INREG %16, 16
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%14:gpr(s64) = G_CONSTANT i64 2
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%10:gpr(s64) = G_SHL %8, %14(s64)
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%11:gpr(p0) = G_PTR_ADD %2, %10(s64)
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%13:gpr(s32) = G_LOAD %11(p0) :: (load 4 from %ir.arrayidx)
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$w0 = COPY %13(s32)
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RET_ReallyLR implicit $w0
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...
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