115 lines
3.3 KiB
Plaintext
115 lines
3.3 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=1 %s -o - | FileCheck %s
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---
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name: add_B
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: add_B
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load 16)
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; CHECK: [[ADDVv16i8v:%[0-9]+]]:fpr8 = ADDVv16i8v [[LDRQui]]
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[ADDVv16i8v]], %subreg.bsub
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; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]
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; CHECK: $w0 = COPY [[COPY1]]
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; CHECK: RET_ReallyLR implicit $w0
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%0:gpr(p0) = COPY $x0
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%1:fpr(<16 x s8>) = G_LOAD %0(p0) :: (load 16)
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%2:fpr(s8) = G_VECREDUCE_ADD %1(<16 x s8>)
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%4:gpr(s8) = COPY %2(s8)
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%3:gpr(s32) = G_ANYEXT %4(s8)
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$w0 = COPY %3(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: add_H
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: add_H
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load 16)
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; CHECK: [[ADDVv8i16v:%[0-9]+]]:fpr16 = ADDVv8i16v [[LDRQui]]
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[ADDVv8i16v]], %subreg.hsub
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; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]
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; CHECK: $w0 = COPY [[COPY1]]
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; CHECK: RET_ReallyLR implicit $w0
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%0:gpr(p0) = COPY $x0
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%1:fpr(<8 x s16>) = G_LOAD %0(p0) :: (load 16)
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%2:fpr(s16) = G_VECREDUCE_ADD %1(<8 x s16>)
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%4:gpr(s16) = COPY %2(s16)
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%3:gpr(s32) = G_ANYEXT %4(s16)
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$w0 = COPY %3(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: add_S
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: add_S
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load 16)
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; CHECK: [[ADDVv4i32v:%[0-9]+]]:fpr32 = ADDVv4i32v [[LDRQui]]
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; CHECK: $w0 = COPY [[ADDVv4i32v]]
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; CHECK: RET_ReallyLR implicit $w0
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%0:gpr(p0) = COPY $x0
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%1:fpr(<4 x s32>) = G_LOAD %0(p0) :: (load 16)
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%2:fpr(s32) = G_VECREDUCE_ADD %1(<4 x s32>)
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$w0 = COPY %2(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: add_D
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: add_D
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load 16)
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; CHECK: [[ADDPv2i64p:%[0-9]+]]:fpr64 = ADDPv2i64p [[LDRQui]]
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; CHECK: $x0 = COPY [[ADDPv2i64p]]
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; CHECK: RET_ReallyLR implicit $x0
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%0:gpr(p0) = COPY $x0
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%1:fpr(<2 x s64>) = G_LOAD %0(p0) :: (load 16)
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%2:fpr(s64) = G_VECREDUCE_ADD %1(<2 x s64>)
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$x0 = COPY %2(s64)
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RET_ReallyLR implicit $x0
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...
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