96 lines
3.2 KiB
Plaintext
96 lines
3.2 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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define void @test_load_i8(i8* %addr) { ret void }
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define void @test_load_i16(i16* %addr) { ret void }
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define void @test_load_i32(i32* %addr) { ret void }
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define void @test_load_i64(i64* %addr) { ret void }
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...
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---
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name: test_load_i8
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: test_load_i8
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[LDXRB:%[0-9]+]]:gpr32 = LDXRB [[COPY]] :: (volatile load 1 from %ir.addr)
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDXRB]], %subreg.sub_32
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; CHECK: $x1 = COPY [[SUBREG_TO_REG]]
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; CHECK: RET_ReallyLR implicit $x1
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%0:gpr(p0) = COPY $x0
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%1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), %0(p0) :: (volatile load 1 from %ir.addr)
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$x1 = COPY %1(s64)
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RET_ReallyLR implicit $x1
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...
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---
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name: test_load_i16
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: test_load_i16
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[LDXRH:%[0-9]+]]:gpr32 = LDXRH [[COPY]] :: (volatile load 2 from %ir.addr)
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDXRH]], %subreg.sub_32
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; CHECK: $x1 = COPY [[SUBREG_TO_REG]]
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; CHECK: RET_ReallyLR implicit $x1
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%0:gpr(p0) = COPY $x0
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%1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), %0(p0) :: (volatile load 2 from %ir.addr)
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$x1 = COPY %1(s64)
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RET_ReallyLR implicit $x1
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...
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---
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name: test_load_i32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: test_load_i32
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[LDXRW:%[0-9]+]]:gpr32 = LDXRW [[COPY]] :: (volatile load 4 from %ir.addr)
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDXRW]], %subreg.sub_32
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; CHECK: $x1 = COPY [[SUBREG_TO_REG]]
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; CHECK: RET_ReallyLR implicit $x1
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%0:gpr(p0) = COPY $x0
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%1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), %0(p0) :: (volatile load 4 from %ir.addr)
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$x1 = COPY %1(s64)
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RET_ReallyLR implicit $x1
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...
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---
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name: test_load_i64
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: test_load_i64
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[LDXRX:%[0-9]+]]:gpr64 = LDXRX [[COPY]] :: (volatile load 8 from %ir.addr)
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; CHECK: $x1 = COPY [[LDXRX]]
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; CHECK: RET_ReallyLR implicit $x1
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%0:gpr(p0) = COPY $x0
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%1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), %0(p0) :: (volatile load 8 from %ir.addr)
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$x1 = COPY %1(s64)
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RET_ReallyLR implicit $x1
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