70 lines
2.4 KiB
Plaintext
70 lines
2.4 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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...
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---
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name: legal_v4s32_v2s32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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- { id: 2, class: fpr }
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frameInfo:
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maxCallFrameSize: 0
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body: |
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bb.0:
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liveins: $d0, $d1
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; CHECK-LABEL: name: legal_v4s32_v2s32
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; CHECK: liveins: $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
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; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.dsub
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; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG1]], 1, [[INSERT_SUBREG]], 0
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; CHECK: $q0 = COPY [[INSvi64lane]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<2 x s32>) = COPY $d0
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%1:fpr(<2 x s32>) = COPY $d1
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%2:fpr(<4 x s32>) = G_CONCAT_VECTORS %0(<2 x s32>), %1(<2 x s32>)
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$q0 = COPY %2(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: legal_v8s16_v4s16
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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- { id: 2, class: fpr }
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frameInfo:
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maxCallFrameSize: 0
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body: |
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bb.0:
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liveins: $d0, $d1
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; CHECK-LABEL: name: legal_v8s16_v4s16
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; CHECK: liveins: $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
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; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.dsub
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; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG1]], 1, [[INSERT_SUBREG]], 0
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; CHECK: $q0 = COPY [[INSvi64lane]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<4 x s16>) = COPY $d0
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%1:fpr(<4 x s16>) = COPY $d1
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%2:fpr(<8 x s16>) = G_CONCAT_VECTORS %0(<4 x s16>), %1(<4 x s16>)
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$q0 = COPY %2(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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