llvm-for-llvmta/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-exten...

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2022-04-25 10:02:23 +02:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-postlegalizer-combiner -global-isel -verify-machineinstrs %s -o - | FileCheck %s
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "aarch64--"
define void @test_zeroext(i8* %addr) {
entry:
ret void
}
define void @test_no_anyext(i8* %addr) {
entry:
ret void
}
...
---
name: test_zeroext
legalized: true
body: |
bb.0.entry:
liveins: $x0
; CHECK-LABEL: name: test_zeroext
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1 from %ir.addr)
; CHECK: $w0 = COPY [[ZEXTLOAD]](s32)
%0:_(p0) = COPY $x0
%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
%2:_(s32) = G_ZEXT %1
$w0 = COPY %2
...
---
name: test_no_anyext
legalized: true
body: |
bb.0.entry:
liveins: $x0
; Check that we don't try to do an anyext combine. We don't want to do this
; because an anyexting load like s64 = G_LOAD %p (load 4) isn't legal.
; CHECK-LABEL: name: test_no_anyext
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.addr)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
; CHECK: $x0 = COPY [[ANYEXT]](s64)
%0:_(p0) = COPY $x0
%1:_(s32) = G_LOAD %0 :: (load 4 from %ir.addr)
%2:_(s64) = G_ANYEXT %1
$x0 = COPY %2
...