249 lines
8.2 KiB
LLVM
249 lines
8.2 KiB
LLVM
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; RUN: opt -analyze -enable-new-pm=0 -scalar-evolution < %s | FileCheck %s
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; RUN: opt -disable-output "-passes=print<scalar-evolution>" < %s 2>&1 | FileCheck %s
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define void @f0(i1 %c) {
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; CHECK-LABEL: Classifying expressions for: @f0
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entry:
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%start = select i1 %c, i32 127, i32 0
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%step = select i1 %c, i32 -1, i32 1
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br label %loop
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loop:
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%loop.iv = phi i32 [ 0, %entry ], [ %loop.iv.inc, %loop ]
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%iv = phi i32 [ %start, %entry ], [ %iv.next, %loop ]
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; CHECK: %iv = phi i32 [ %start, %entry ], [ %iv.next, %loop ]
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; CHECK-NEXT: --> {%start,+,%step}<%loop> U: [0,128) S: [0,128)
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%iv.next = add i32 %iv, %step
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%loop.iv.inc = add i32 %loop.iv, 1
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%be.cond = icmp ne i32 %loop.iv.inc, 128
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br i1 %be.cond, label %loop, label %leave
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leave:
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ret void
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}
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define void @f1(i1 %c) {
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; CHECK-LABEL: Classifying expressions for: @f1
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entry:
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%start = select i1 %c, i32 120, i32 0
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%step = select i1 %c, i32 -8, i32 8
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br label %loop
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loop:
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%loop.iv = phi i32 [ 0, %entry ], [ %loop.iv.inc, %loop ]
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%iv = phi i32 [ %start, %entry ], [ %iv.next, %loop ]
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; CHECK: %iv.1 = add i32 %iv, 1
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; CHECK-NEXT: --> {(1 + %start)<nuw><nsw>,+,%step}<%loop> U: [1,122) S: [1,122)
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; CHECK: %iv.2 = add i32 %iv, 2
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; CHECK-NEXT: --> {(2 + %start)<nuw><nsw>,+,%step}<%loop> U: [2,123) S: [2,123)
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; CHECK: %iv.3 = add i32 %iv, 3
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; CHECK-NEXT: --> {(3 + %start)<nuw><nsw>,+,%step}<%loop> U: [3,124) S: [3,124)
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; CHECK: %iv.4 = add i32 %iv, 4
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; CHECK-NEXT: --> {(4 + %start)<nuw><nsw>,+,%step}<%loop> U: [4,125) S: [4,125)
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; CHECK: %iv.5 = add i32 %iv, 5
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; CHECK-NEXT: --> {(5 + %start)<nuw><nsw>,+,%step}<%loop> U: [5,126) S: [5,126)
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; CHECK: %iv.6 = add i32 %iv, 6
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; CHECK-NEXT: --> {(6 + %start)<nuw><nsw>,+,%step}<%loop> U: [6,127) S: [6,127)
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; CHECK: %iv.7 = add i32 %iv, 7
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; CHECK-NEXT: --> {(7 + %start)<nuw><nsw>,+,%step}<%loop> U: [7,128) S: [7,128)
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%iv.1 = add i32 %iv, 1
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%iv.2 = add i32 %iv, 2
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%iv.3 = add i32 %iv, 3
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%iv.4 = add i32 %iv, 4
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%iv.5 = add i32 %iv, 5
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%iv.6 = add i32 %iv, 6
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%iv.7 = add i32 %iv, 7
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; CHECK: %iv.m1 = sub i32 %iv, 1
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; CHECK-NEXT: --> {(-1 + %start)<nsw>,+,%step}<%loop> U: [-1,120) S: [-1,120)
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; CHECK: %iv.m2 = sub i32 %iv, 2
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; CHECK-NEXT: --> {(-2 + %start)<nsw>,+,%step}<%loop> U: [0,-1) S: [-2,119)
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; CHECK: %iv.m3 = sub i32 %iv, 3
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; CHECK-NEXT: --> {(-3 + %start)<nsw>,+,%step}<%loop> U: [-3,118) S: [-3,118)
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; CHECK: %iv.m4 = sub i32 %iv, 4
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; CHECK-NEXT: --> {(-4 + %start)<nsw>,+,%step}<%loop> U: [0,-3) S: [-4,117)
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; CHECK: %iv.m5 = sub i32 %iv, 5
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; CHECK-NEXT: --> {(-5 + %start)<nsw>,+,%step}<%loop> U: [-5,116) S: [-5,116)
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; CHECK: %iv.m6 = sub i32 %iv, 6
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; CHECK-NEXT: --> {(-6 + %start)<nsw>,+,%step}<%loop> U: [0,-1) S: [-6,115)
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; CHECK: %iv.m7 = sub i32 %iv, 7
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; CHECK-NEXT: --> {(-7 + %start)<nsw>,+,%step}<%loop> U: [-7,114) S: [-7,114)
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%iv.m1 = sub i32 %iv, 1
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%iv.m2 = sub i32 %iv, 2
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%iv.m3 = sub i32 %iv, 3
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%iv.m4 = sub i32 %iv, 4
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%iv.m5 = sub i32 %iv, 5
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%iv.m6 = sub i32 %iv, 6
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%iv.m7 = sub i32 %iv, 7
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%iv.next = add i32 %iv, %step
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%loop.iv.inc = add i32 %loop.iv, 1
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%be.cond = icmp sgt i32 %loop.iv, 14
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br i1 %be.cond, label %leave, label %loop
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leave:
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ret void
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}
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define void @f2(i1 %c) {
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; CHECK-LABEL: Classifying expressions for: @f2
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entry:
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%start = select i1 %c, i32 127, i32 0
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%step = select i1 %c, i32 -1, i32 1
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br label %loop
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loop:
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%loop.iv = phi i32 [ 0, %entry ], [ %loop.iv.inc, %loop ]
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%iv = phi i32 [ %start, %entry ], [ %iv.next, %loop ]
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%iv.sext = sext i32 %iv to i64
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%iv.next = add i32 %iv, %step
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; CHECK: %iv.sext = sext i32 %iv to i64
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; CHECK-NEXT: --> {(sext i32 %start to i64),+,(sext i32 %step to i64)}<nsw><%loop> U: [0,128) S: [0,128)
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%loop.iv.inc = add i32 %loop.iv, 1
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%be.cond = icmp ne i32 %loop.iv.inc, 128
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br i1 %be.cond, label %loop, label %leave
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leave:
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ret void
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}
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define void @f3(i1 %c) {
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; CHECK-LABEL: Classifying expressions for: @f3
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entry:
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; NB! the i16 type (as opposed to i32), the choice of the constant 509
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; and the trip count are all related and not arbitrary. We want an
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; add recurrence that will look like it can unsign-overflow *unless*
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; SCEV is able to see the correlation between the two selects feeding
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; into the initial value and the step increment.
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%start = select i1 %c, i16 1000, i16 0
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%step = select i1 %c, i16 1, i16 509
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br label %loop
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loop:
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%loop.iv = phi i16 [ 0, %entry ], [ %loop.iv.inc, %loop ]
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%iv = phi i16 [ %start, %entry ], [ %iv.next, %loop ]
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%iv.zext = zext i16 %iv to i64
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; CHECK: %iv.zext = zext i16 %iv to i64
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; CHECK-NEXT: --> {(zext i16 %start to i64),+,(zext i16 %step to i64)}<nuw><%loop> U: [0,64644) S: [0,64644)
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%iv.next = add i16 %iv, %step
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%loop.iv.inc = add i16 %loop.iv, 1
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%be.cond = icmp ne i16 %loop.iv.inc, 128
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br i1 %be.cond, label %loop, label %leave
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leave:
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ret void
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}
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define void @f4(i1 %c) {
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; CHECK-LABEL: Classifying expressions for: @f4
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; @f4() demonstrates a case where SCEV is not able to compute a
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; precise range for %iv.trunc, though it should be able to, in theory.
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; This is because SCEV looks into affine add recurrences only when the
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; backedge taken count of the loop has the same bitwidth as the
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; induction variable.
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entry:
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%start = select i1 %c, i32 127, i32 0
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%step = select i1 %c, i32 -1, i32 1
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br label %loop
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loop:
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%loop.iv = phi i32 [ 0, %entry ], [ %loop.iv.inc, %loop ]
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%iv = phi i32 [ %start, %entry ], [ %iv.next, %loop ]
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%iv.trunc = trunc i32 %iv to i16
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; CHECK: %iv.trunc = trunc i32 %iv to i16
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; CHECK-NEXT: --> {(trunc i32 %start to i16),+,(trunc i32 %step to i16)}<%loop> U: full-set S: full-set
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%iv.next = add i32 %iv, %step
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%loop.iv.inc = add i32 %loop.iv, 1
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%be.cond = icmp ne i32 %loop.iv.inc, 128
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br i1 %be.cond, label %loop, label %leave
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leave:
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ret void
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}
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define void @f5(i1 %c) {
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; CHECK-LABEL: Classifying expressions for: @f5
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entry:
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%start = select i1 %c, i32 127, i32 0
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%step = select i1 %c, i32 -1, i32 1
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br label %loop
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loop:
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%loop.iv = phi i16 [ 0, %entry ], [ %loop.iv.inc, %loop ]
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%iv = phi i32 [ %start, %entry ], [ %iv.next, %loop ]
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%iv.trunc = trunc i32 %iv to i16
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; CHECK: %iv.trunc = trunc i32 %iv to i16
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; CHECK-NEXT: --> {(trunc i32 %start to i16),+,(trunc i32 %step to i16)}<%loop> U: [0,128) S: [0,128)
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%iv.next = add i32 %iv, %step
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%loop.iv.inc = add i16 %loop.iv, 1
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%be.cond = icmp ne i16 %loop.iv.inc, 128
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br i1 %be.cond, label %loop, label %leave
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leave:
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ret void
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}
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define void @f6(i1 %c) {
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; CHECK-LABEL: Classifying expressions for: @f6
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entry:
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%start = select i1 %c, i32 127, i32 0
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%step = select i1 %c, i32 -2, i32 0
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br label %loop
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loop:
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%loop.iv = phi i16 [ 0, %entry ], [ %loop.iv.inc, %loop ]
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%iv = phi i32 [ %start, %entry ], [ %iv.next, %loop ]
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; CHECK: %iv = phi i32 [ %start, %entry ], [ %iv.next, %loop ]
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; CHECK-NEXT: --> {%start,+,(1 + %step)<nuw><nsw>}<%loop> U: [0,128) S: [0,128)
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%step.plus.one = add i32 %step, 1
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%iv.next = add i32 %iv, %step.plus.one
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%iv.sext = sext i32 %iv to i64
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; CHECK: %iv.sext = sext i32 %iv to i64
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; CHECK-NEXT: --> {(sext i32 %start to i64),+,(1 + (sext i32 %step to i64))<nuw><nsw>}<nsw><%loop> U: [0,128) S: [0,128)
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%loop.iv.inc = add i16 %loop.iv, 1
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%be.cond = icmp ne i16 %loop.iv.inc, 128
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br i1 %be.cond, label %loop, label %leave
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leave:
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ret void
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}
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define void @f7(i1 %c) {
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; CHECK-LABEL: Classifying expressions for: @f7
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entry:
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%start = select i1 %c, i32 127, i32 0
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%step = select i1 %c, i32 -1, i32 1
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br label %loop
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loop:
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%loop.iv = phi i16 [ 0, %entry ], [ %loop.iv.inc, %loop ]
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%iv = phi i32 [ %start, %entry ], [ %iv.next, %loop ]
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%iv.trunc = trunc i32 %iv to i16
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; CHECK: %iv.trunc = trunc i32 %iv to i16
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; CHECK-NEXT: --> {(trunc i32 %start to i16),+,(trunc i32 %step to i16)}<%loop> U: [0,128) S: [0,128)
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%iv.next = add i32 %iv, %step
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%iv.trunc.plus.one = add i16 %iv.trunc, 1
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; CHECK: %iv.trunc.plus.one = add i16 %iv.trunc, 1
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; CHECK-NEXT: --> {(1 + (trunc i32 %start to i16))<nuw><nsw>,+,(trunc i32 %step to i16)}<%loop> U: [1,129) S: [1,129)
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%iv.trunc.plus.two = add i16 %iv.trunc, 2
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; CHECK: %iv.trunc.plus.two = add i16 %iv.trunc, 2
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; CHECK-NEXT: --> {(2 + (trunc i32 %start to i16))<nuw><nsw>,+,(trunc i32 %step to i16)}<%loop> U: [2,130) S: [2,130)
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%loop.iv.inc = add i16 %loop.iv, 1
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%be.cond = icmp ne i16 %loop.iv.inc, 128
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br i1 %be.cond, label %loop, label %leave
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leave:
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ret void
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}
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