103 lines
4.2 KiB
LLVM
103 lines
4.2 KiB
LLVM
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; RUN: opt -mtriple=amdgcn-mesa-mesa3d -analyze -divergence -use-gpu-divergence-analysis %s | FileCheck %s
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; Tests control flow intrinsics that should be treated as uniform
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; CHECK: Printing analysis 'Legacy Divergence Analysis' for function 'test_if_break':
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; CHECK: DIVERGENT: %cond = icmp eq i32 %arg0, 0
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; CHECK-NOT: DIVERGENT
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; CHECK: ret void
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define amdgpu_ps void @test_if_break(i32 %arg0, i64 inreg %saved) {
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entry:
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%cond = icmp eq i32 %arg0, 0
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%break = call i64 @llvm.amdgcn.if.break.i64.i64(i1 %cond, i64 %saved)
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store volatile i64 %break, i64 addrspace(1)* undef
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ret void
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}
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; CHECK: Printing analysis 'Legacy Divergence Analysis' for function 'test_if':
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; CHECK: DIVERGENT: %cond = icmp eq i32 %arg0, 0
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; CHECK-NEXT: DIVERGENT: %if = call { i1, i64 } @llvm.amdgcn.if.i64(i1 %cond)
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; CHECK-NEXT: DIVERGENT: %if.bool = extractvalue { i1, i64 } %if, 0
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; CHECK-NOT: DIVERGENT
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; CHECK: DIVERGENT: %if.bool.ext = zext i1 %if.bool to i32
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define void @test_if(i32 %arg0) {
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entry:
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%cond = icmp eq i32 %arg0, 0
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%if = call { i1, i64 } @llvm.amdgcn.if.i64(i1 %cond)
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%if.bool = extractvalue { i1, i64 } %if, 0
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%if.mask = extractvalue { i1, i64 } %if, 1
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%if.bool.ext = zext i1 %if.bool to i32
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store volatile i32 %if.bool.ext, i32 addrspace(1)* undef
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store volatile i64 %if.mask, i64 addrspace(1)* undef
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ret void
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}
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; The result should still be treated as divergent, even with a uniform source.
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; CHECK: Printing analysis 'Legacy Divergence Analysis' for function 'test_if_uniform':
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; CHECK-NOT: DIVERGENT
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; CHECK: DIVERGENT: %if = call { i1, i64 } @llvm.amdgcn.if.i64(i1 %cond)
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; CHECK-NEXT: DIVERGENT: %if.bool = extractvalue { i1, i64 } %if, 0
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; CHECK-NOT: DIVERGENT
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; CHECK: DIVERGENT: %if.bool.ext = zext i1 %if.bool to i32
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define amdgpu_ps void @test_if_uniform(i32 inreg %arg0) {
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entry:
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%cond = icmp eq i32 %arg0, 0
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%if = call { i1, i64 } @llvm.amdgcn.if.i64(i1 %cond)
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%if.bool = extractvalue { i1, i64 } %if, 0
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%if.mask = extractvalue { i1, i64 } %if, 1
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%if.bool.ext = zext i1 %if.bool to i32
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store volatile i32 %if.bool.ext, i32 addrspace(1)* undef
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store volatile i64 %if.mask, i64 addrspace(1)* undef
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ret void
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}
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; CHECK: Printing analysis 'Legacy Divergence Analysis' for function 'test_loop_uniform':
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; CHECK: DIVERGENT: %loop = call i1 @llvm.amdgcn.loop.i64(i64 %mask)
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define amdgpu_ps void @test_loop_uniform(i64 inreg %mask) {
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entry:
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%loop = call i1 @llvm.amdgcn.loop.i64(i64 %mask)
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%loop.ext = zext i1 %loop to i32
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store volatile i32 %loop.ext, i32 addrspace(1)* undef
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ret void
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}
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; CHECK: Printing analysis 'Legacy Divergence Analysis' for function 'test_else':
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; CHECK: DIVERGENT: %else = call { i1, i64 } @llvm.amdgcn.else.i64.i64(i64 %mask)
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; CHECK: DIVERGENT: %else.bool = extractvalue { i1, i64 } %else, 0
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; CHECK: {{^[ \t]+}}%else.mask = extractvalue { i1, i64 } %else, 1
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define amdgpu_ps void @test_else(i64 inreg %mask) {
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entry:
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%else = call { i1, i64 } @llvm.amdgcn.else.i64.i64(i64 %mask)
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%else.bool = extractvalue { i1, i64 } %else, 0
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%else.mask = extractvalue { i1, i64 } %else, 1
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%else.bool.ext = zext i1 %else.bool to i32
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store volatile i32 %else.bool.ext, i32 addrspace(1)* undef
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store volatile i64 %else.mask, i64 addrspace(1)* undef
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ret void
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}
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; This case is probably always broken
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; CHECK: Printing analysis 'Legacy Divergence Analysis' for function 'test_else_divergent_mask':
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; CHECK: DIVERGENT: %if = call { i1, i64 } @llvm.amdgcn.else.i64.i64(i64 %mask)
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; CHECK-NEXT: DIVERGENT: %if.bool = extractvalue { i1, i64 } %if, 0
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; CHECK-NOT: DIVERGENT
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; CHECK: DIVERGENT: %if.bool.ext = zext i1 %if.bool to i32
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define void @test_else_divergent_mask(i64 %mask) {
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entry:
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%if = call { i1, i64 } @llvm.amdgcn.else.i64.i64(i64 %mask)
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%if.bool = extractvalue { i1, i64 } %if, 0
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%if.mask = extractvalue { i1, i64 } %if, 1
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%if.bool.ext = zext i1 %if.bool to i32
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store volatile i32 %if.bool.ext, i32 addrspace(1)* undef
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store volatile i64 %if.mask, i64 addrspace(1)* undef
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ret void
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}
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declare { i1, i64 } @llvm.amdgcn.if.i64(i1) #0
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declare { i1, i64 } @llvm.amdgcn.else.i64.i64(i64) #0
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declare i64 @llvm.amdgcn.if.break.i64.i64(i1, i64) #1
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declare i1 @llvm.amdgcn.loop.i64(i64) #1
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attributes #0 = { convergent nounwind }
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attributes #1 = { convergent nounwind readnone }
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