112 lines
5.1 KiB
LLVM
112 lines
5.1 KiB
LLVM
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; RUN: opt -mtriple amdgcn-unknown-amdhsa -analyze -divergence -use-gpu-divergence-analysis %s | FileCheck %s
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declare i32 @gf2(i32)
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declare i32 @gf1(i32)
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define void @tw1(i32 addrspace(4)* noalias nocapture readonly %A, i32 addrspace(4)* noalias nocapture %B) local_unnamed_addr #2 {
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; CHECK: Printing analysis 'Legacy Divergence Analysis' for function 'tw1':
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; CHECK: DIVERGENT: i32 addrspace(4)* %A
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; CHECK: DIVERGENT: i32 addrspace(4)* %B
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entry:
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; CHECK: DIVERGENT: %call = tail call i32 @gf2(i32 0) #0
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; CHECK: DIVERGENT: %cmp = icmp ult i32 %call, 16
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; CHECK: DIVERGENT: br i1 %cmp, label %if.then, label %new_exit
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%call = tail call i32 @gf2(i32 0) #3
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%cmp = icmp ult i32 %call, 16
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br i1 %cmp, label %if.then, label %new_exit
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if.then:
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; CHECK: DIVERGENT: %call1 = tail call i32 @gf1(i32 0) #0
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; CHECK: DIVERGENT: %arrayidx = getelementptr inbounds i32, i32 addrspace(4)* %A, i32 %call1
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; CHECK: DIVERGENT: %0 = load i32, i32 addrspace(4)* %arrayidx, align 4
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; CHECK: DIVERGENT: %cmp225 = icmp sgt i32 %0, 0
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; CHECK: DIVERGENT: %arrayidx10 = getelementptr inbounds i32, i32 addrspace(4)* %B, i32 %call1
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; CHECK: DIVERGENT: br i1 %cmp225, label %while.body.preheader, label %if.then.while.end_crit_edge
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%call1 = tail call i32 @gf1(i32 0) #4
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%arrayidx = getelementptr inbounds i32, i32 addrspace(4)* %A, i32 %call1
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%0 = load i32, i32 addrspace(4)* %arrayidx, align 4
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%cmp225 = icmp sgt i32 %0, 0
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%arrayidx10 = getelementptr inbounds i32, i32 addrspace(4)* %B, i32 %call1
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br i1 %cmp225, label %while.body.preheader, label %if.then.while.end_crit_edge
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while.body.preheader:
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br label %while.body
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if.then.while.end_crit_edge:
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; CHECK: DIVERGENT: %.pre = load i32, i32 addrspace(4)* %arrayidx10, align 4
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%.pre = load i32, i32 addrspace(4)* %arrayidx10, align 4
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br label %while.end
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while.body:
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; CHECK-NOT: DIVERGENT: %i.026 = phi i32 [ %inc, %if.end.while.body_crit_edge ], [ 0, %while.body.preheader ]
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; CHECK: DIVERGENT: %call3 = tail call i32 @gf1(i32 0) #0
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; CHECK: DIVERGENT: %cmp4 = icmp ult i32 %call3, 10
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; CHECK: DIVERGENT: %arrayidx6 = getelementptr inbounds i32, i32 addrspace(4)* %A, i32 %i.026
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; CHECK: DIVERGENT: %1 = load i32, i32 addrspace(4)* %arrayidx6, align 4
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; CHECK: DIVERGENT: br i1 %cmp4, label %if.then5, label %if.else
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%i.026 = phi i32 [ %inc, %if.end.while.body_crit_edge ], [ 0, %while.body.preheader ]
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%call3 = tail call i32 @gf1(i32 0) #4
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%cmp4 = icmp ult i32 %call3, 10
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%arrayidx6 = getelementptr inbounds i32, i32 addrspace(4)* %A, i32 %i.026
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%1 = load i32, i32 addrspace(4)* %arrayidx6, align 4
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br i1 %cmp4, label %if.then5, label %if.else
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if.then5:
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; CHECK: DIVERGENT: %mul = shl i32 %1, 1
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; CHECK: DIVERGENT: %2 = load i32, i32 addrspace(4)* %arrayidx10, align 4
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; CHECK: DIVERGENT: %add = add nsw i32 %2, %mul
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%mul = shl i32 %1, 1
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%2 = load i32, i32 addrspace(4)* %arrayidx10, align 4
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%add = add nsw i32 %2, %mul
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br label %if.end
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if.else:
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; CHECK: DIVERGENT: %mul9 = shl i32 %1, 2
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; CHECK: DIVERGENT: %3 = load i32, i32 addrspace(4)* %arrayidx10, align 4
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; CHECK: DIVERGENT: %add11 = add nsw i32 %3, %mul9
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%mul9 = shl i32 %1, 2
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%3 = load i32, i32 addrspace(4)* %arrayidx10, align 4
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%add11 = add nsw i32 %3, %mul9
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br label %if.end
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if.end:
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; CHECK: DIVERGENT: %storemerge = phi i32 [ %add11, %if.else ], [ %add, %if.then5 ]
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; CHECK: DIVERGENT: store i32 %storemerge, i32 addrspace(4)* %arrayidx10, align 4
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; CHECK-NOT: DIVERGENT: %inc = add nuw nsw i32 %i.026, 1
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; CHECK: DIVERGENT: %exitcond = icmp ne i32 %inc, %0
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; CHECK: DIVERGENT: br i1 %exitcond, label %if.end.while.body_crit_edge, label %while.end.loopexit
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%storemerge = phi i32 [ %add11, %if.else ], [ %add, %if.then5 ]
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store i32 %storemerge, i32 addrspace(4)* %arrayidx10, align 4
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%inc = add nuw nsw i32 %i.026, 1
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%exitcond = icmp ne i32 %inc, %0
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br i1 %exitcond, label %if.end.while.body_crit_edge, label %while.end.loopexit
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if.end.while.body_crit_edge:
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br label %while.body
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while.end.loopexit:
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; CHECK: DIVERGENT: %storemerge.lcssa = phi i32 [ %storemerge, %if.end ]
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%storemerge.lcssa = phi i32 [ %storemerge, %if.end ]
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br label %while.end
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while.end:
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; CHECK: DIVERGENT: %4 = phi i32 [ %.pre, %if.then.while.end_crit_edge ], [ %storemerge.lcssa, %while.end.loopexit ]
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; CHECK: DIVERGENT: %i.0.lcssa = phi i32 [ 0, %if.then.while.end_crit_edge ], [ %0, %while.end.loopexit ]
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; CHECK: DIVERGENT: %sub = sub nsw i32 %4, %i.0.lcssa
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; CHECK: DIVERGENT: store i32 %sub, i32 addrspace(4)* %arrayidx10, align 4
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%4 = phi i32 [ %.pre, %if.then.while.end_crit_edge ], [ %storemerge.lcssa, %while.end.loopexit ]
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%i.0.lcssa = phi i32 [ 0, %if.then.while.end_crit_edge ], [ %0, %while.end.loopexit ]
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%sub = sub nsw i32 %4, %i.0.lcssa
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store i32 %sub, i32 addrspace(4)* %arrayidx10, align 4
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br label %new_exit
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new_exit:
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind readnone }
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attributes #3 = { nounwind readnone }
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attributes #4 = { nounwind readnone }
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