46 lines
2.2 KiB
LLVM
46 lines
2.2 KiB
LLVM
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; RUN: opt -mtriple=amdgcn-- -analyze -divergence -use-gpu-divergence-analysis %s | FileCheck %s
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; CHECK: DIVERGENT: %orig = atomicrmw xchg i32* %ptr, i32 %val seq_cst
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define i32 @test1(i32* %ptr, i32 %val) #0 {
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%orig = atomicrmw xchg i32* %ptr, i32 %val seq_cst
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ret i32 %orig
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}
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; CHECK: DIVERGENT: %orig = cmpxchg i32* %ptr, i32 %cmp, i32 %new seq_cst seq_cst
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define {i32, i1} @test2(i32* %ptr, i32 %cmp, i32 %new) {
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%orig = cmpxchg i32* %ptr, i32 %cmp, i32 %new seq_cst seq_cst
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ret {i32, i1} %orig
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}
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; CHECK: DIVERGENT: %ret = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %ptr, i32 %val, i32 0, i32 0, i1 false)
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define i32 @test_atomic_inc_i32(i32 addrspace(1)* %ptr, i32 %val) #0 {
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%ret = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %ptr, i32 %val, i32 0, i32 0, i1 false)
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ret i32 %ret
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}
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; CHECK: DIVERGENT: %ret = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %ptr, i64 %val, i32 0, i32 0, i1 false)
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define i64 @test_atomic_inc_i64(i64 addrspace(1)* %ptr, i64 %val) #0 {
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%ret = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %ptr, i64 %val, i32 0, i32 0, i1 false)
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ret i64 %ret
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}
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; CHECK: DIVERGENT: %ret = call i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* %ptr, i32 %val, i32 0, i32 0, i1 false)
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define i32 @test_atomic_dec_i32(i32 addrspace(1)* %ptr, i32 %val) #0 {
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%ret = call i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* %ptr, i32 %val, i32 0, i32 0, i1 false)
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ret i32 %ret
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}
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; CHECK: DIVERGENT: %ret = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %ptr, i64 %val, i32 0, i32 0, i1 false)
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define i64 @test_atomic_dec_i64(i64 addrspace(1)* %ptr, i64 %val) #0 {
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%ret = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %ptr, i64 %val, i32 0, i32 0, i1 false)
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ret i64 %ret
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}
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declare i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* nocapture, i32, i32, i32, i1) #1
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declare i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* nocapture, i64, i32, i32, i1) #1
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declare i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* nocapture, i32, i32, i32, i1) #1
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declare i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* nocapture, i64, i32, i32, i1) #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind argmemonly }
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