40 lines
1.3 KiB
TableGen
40 lines
1.3 KiB
TableGen
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//===- X86InstrTDX.td - TDX Instruction Set Extension -*- tablegen -*===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the instructions that make up the Intel TDX instruction
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// set.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// TDX instructions
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// 64-bit only instructions
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let SchedRW = [WriteSystem], Predicates = [In64BitMode] in {
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// SEAMCALL - Call to SEAM VMX-root Operation Module
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def SEAMCALL : I<0x01, MRM_CF, (outs), (ins),
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"seamcall", []>, PD;
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// SEAMRET - Return to Legacy VMX-root Operation
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def SEAMRET : I<0x01, MRM_CD, (outs), (ins),
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"seamret", []>, PD;
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// SEAMOPS - SEAM Operations
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def SEAMOPS : I<0x01, MRM_CE, (outs), (ins),
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"seamops", []>, PD;
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} // SchedRW
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// common instructions
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let SchedRW = [WriteSystem] in {
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// TDCALL - Call SEAM Module Functions
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def TDCALL : I<0x01, MRM_CC, (outs), (ins),
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"tdcall", []>, PD;
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} // SchedRW
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