648 lines
16 KiB
C
648 lines
16 KiB
C
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//===-- X86DisassemblerDecoderInternal.h - Disassembler decoder -*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is part of the X86 Disassembler.
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// It contains the public interface of the instruction decoder.
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// Documentation for the disassembler can be found in X86Disassembler.h.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLERDECODER_H
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#define LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLERDECODER_H
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/Support/X86DisassemblerDecoderCommon.h"
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namespace llvm {
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namespace X86Disassembler {
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// Accessor functions for various fields of an Intel instruction
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#define modFromModRM(modRM) (((modRM) & 0xc0) >> 6)
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#define regFromModRM(modRM) (((modRM) & 0x38) >> 3)
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#define rmFromModRM(modRM) ((modRM) & 0x7)
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#define scaleFromSIB(sib) (((sib) & 0xc0) >> 6)
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#define indexFromSIB(sib) (((sib) & 0x38) >> 3)
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#define baseFromSIB(sib) ((sib) & 0x7)
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#define wFromREX(rex) (((rex) & 0x8) >> 3)
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#define rFromREX(rex) (((rex) & 0x4) >> 2)
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#define xFromREX(rex) (((rex) & 0x2) >> 1)
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#define bFromREX(rex) ((rex) & 0x1)
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#define rFromEVEX2of4(evex) (((~(evex)) & 0x80) >> 7)
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#define xFromEVEX2of4(evex) (((~(evex)) & 0x40) >> 6)
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#define bFromEVEX2of4(evex) (((~(evex)) & 0x20) >> 5)
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#define r2FromEVEX2of4(evex) (((~(evex)) & 0x10) >> 4)
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#define mmFromEVEX2of4(evex) ((evex) & 0x3)
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#define wFromEVEX3of4(evex) (((evex) & 0x80) >> 7)
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#define vvvvFromEVEX3of4(evex) (((~(evex)) & 0x78) >> 3)
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#define ppFromEVEX3of4(evex) ((evex) & 0x3)
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#define zFromEVEX4of4(evex) (((evex) & 0x80) >> 7)
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#define l2FromEVEX4of4(evex) (((evex) & 0x40) >> 6)
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#define lFromEVEX4of4(evex) (((evex) & 0x20) >> 5)
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#define bFromEVEX4of4(evex) (((evex) & 0x10) >> 4)
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#define v2FromEVEX4of4(evex) (((~evex) & 0x8) >> 3)
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#define aaaFromEVEX4of4(evex) ((evex) & 0x7)
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#define rFromVEX2of3(vex) (((~(vex)) & 0x80) >> 7)
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#define xFromVEX2of3(vex) (((~(vex)) & 0x40) >> 6)
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#define bFromVEX2of3(vex) (((~(vex)) & 0x20) >> 5)
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#define mmmmmFromVEX2of3(vex) ((vex) & 0x1f)
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#define wFromVEX3of3(vex) (((vex) & 0x80) >> 7)
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#define vvvvFromVEX3of3(vex) (((~(vex)) & 0x78) >> 3)
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#define lFromVEX3of3(vex) (((vex) & 0x4) >> 2)
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#define ppFromVEX3of3(vex) ((vex) & 0x3)
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#define rFromVEX2of2(vex) (((~(vex)) & 0x80) >> 7)
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#define vvvvFromVEX2of2(vex) (((~(vex)) & 0x78) >> 3)
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#define lFromVEX2of2(vex) (((vex) & 0x4) >> 2)
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#define ppFromVEX2of2(vex) ((vex) & 0x3)
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#define rFromXOP2of3(xop) (((~(xop)) & 0x80) >> 7)
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#define xFromXOP2of3(xop) (((~(xop)) & 0x40) >> 6)
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#define bFromXOP2of3(xop) (((~(xop)) & 0x20) >> 5)
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#define mmmmmFromXOP2of3(xop) ((xop) & 0x1f)
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#define wFromXOP3of3(xop) (((xop) & 0x80) >> 7)
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#define vvvvFromXOP3of3(vex) (((~(vex)) & 0x78) >> 3)
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#define lFromXOP3of3(xop) (((xop) & 0x4) >> 2)
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#define ppFromXOP3of3(xop) ((xop) & 0x3)
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// These enums represent Intel registers for use by the decoder.
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#define REGS_8BIT \
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ENTRY(AL) \
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ENTRY(CL) \
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ENTRY(DL) \
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ENTRY(BL) \
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ENTRY(AH) \
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ENTRY(CH) \
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ENTRY(DH) \
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ENTRY(BH) \
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ENTRY(R8B) \
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ENTRY(R9B) \
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ENTRY(R10B) \
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ENTRY(R11B) \
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ENTRY(R12B) \
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ENTRY(R13B) \
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ENTRY(R14B) \
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ENTRY(R15B) \
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ENTRY(SPL) \
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ENTRY(BPL) \
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ENTRY(SIL) \
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ENTRY(DIL)
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#define EA_BASES_16BIT \
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ENTRY(BX_SI) \
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ENTRY(BX_DI) \
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ENTRY(BP_SI) \
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ENTRY(BP_DI) \
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ENTRY(SI) \
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ENTRY(DI) \
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ENTRY(BP) \
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ENTRY(BX) \
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ENTRY(R8W) \
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ENTRY(R9W) \
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ENTRY(R10W) \
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ENTRY(R11W) \
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ENTRY(R12W) \
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ENTRY(R13W) \
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ENTRY(R14W) \
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ENTRY(R15W)
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#define REGS_16BIT \
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ENTRY(AX) \
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ENTRY(CX) \
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ENTRY(DX) \
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ENTRY(BX) \
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ENTRY(SP) \
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ENTRY(BP) \
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ENTRY(SI) \
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ENTRY(DI) \
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ENTRY(R8W) \
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ENTRY(R9W) \
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ENTRY(R10W) \
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ENTRY(R11W) \
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ENTRY(R12W) \
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ENTRY(R13W) \
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ENTRY(R14W) \
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ENTRY(R15W)
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#define EA_BASES_32BIT \
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ENTRY(EAX) \
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ENTRY(ECX) \
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ENTRY(EDX) \
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ENTRY(EBX) \
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ENTRY(sib) \
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ENTRY(EBP) \
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ENTRY(ESI) \
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ENTRY(EDI) \
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ENTRY(R8D) \
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ENTRY(R9D) \
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ENTRY(R10D) \
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ENTRY(R11D) \
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ENTRY(R12D) \
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ENTRY(R13D) \
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ENTRY(R14D) \
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ENTRY(R15D)
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#define REGS_32BIT \
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ENTRY(EAX) \
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ENTRY(ECX) \
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ENTRY(EDX) \
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ENTRY(EBX) \
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ENTRY(ESP) \
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ENTRY(EBP) \
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ENTRY(ESI) \
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ENTRY(EDI) \
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ENTRY(R8D) \
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ENTRY(R9D) \
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ENTRY(R10D) \
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ENTRY(R11D) \
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ENTRY(R12D) \
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ENTRY(R13D) \
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ENTRY(R14D) \
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ENTRY(R15D)
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#define EA_BASES_64BIT \
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ENTRY(RAX) \
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ENTRY(RCX) \
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ENTRY(RDX) \
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ENTRY(RBX) \
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ENTRY(sib64) \
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ENTRY(RBP) \
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ENTRY(RSI) \
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ENTRY(RDI) \
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ENTRY(R8) \
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ENTRY(R9) \
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ENTRY(R10) \
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ENTRY(R11) \
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ENTRY(R12) \
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ENTRY(R13) \
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ENTRY(R14) \
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ENTRY(R15)
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#define REGS_64BIT \
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ENTRY(RAX) \
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ENTRY(RCX) \
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ENTRY(RDX) \
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ENTRY(RBX) \
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ENTRY(RSP) \
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ENTRY(RBP) \
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ENTRY(RSI) \
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ENTRY(RDI) \
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ENTRY(R8) \
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ENTRY(R9) \
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ENTRY(R10) \
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ENTRY(R11) \
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ENTRY(R12) \
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ENTRY(R13) \
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ENTRY(R14) \
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ENTRY(R15)
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#define REGS_MMX \
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ENTRY(MM0) \
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ENTRY(MM1) \
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ENTRY(MM2) \
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ENTRY(MM3) \
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ENTRY(MM4) \
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ENTRY(MM5) \
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ENTRY(MM6) \
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ENTRY(MM7)
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#define REGS_XMM \
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ENTRY(XMM0) \
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ENTRY(XMM1) \
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ENTRY(XMM2) \
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ENTRY(XMM3) \
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ENTRY(XMM4) \
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ENTRY(XMM5) \
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ENTRY(XMM6) \
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ENTRY(XMM7) \
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ENTRY(XMM8) \
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ENTRY(XMM9) \
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ENTRY(XMM10) \
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ENTRY(XMM11) \
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ENTRY(XMM12) \
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ENTRY(XMM13) \
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ENTRY(XMM14) \
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ENTRY(XMM15) \
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ENTRY(XMM16) \
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ENTRY(XMM17) \
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ENTRY(XMM18) \
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ENTRY(XMM19) \
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ENTRY(XMM20) \
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ENTRY(XMM21) \
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ENTRY(XMM22) \
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ENTRY(XMM23) \
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ENTRY(XMM24) \
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ENTRY(XMM25) \
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ENTRY(XMM26) \
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ENTRY(XMM27) \
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ENTRY(XMM28) \
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ENTRY(XMM29) \
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ENTRY(XMM30) \
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ENTRY(XMM31)
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#define REGS_YMM \
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ENTRY(YMM0) \
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ENTRY(YMM1) \
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ENTRY(YMM2) \
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ENTRY(YMM3) \
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ENTRY(YMM4) \
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ENTRY(YMM5) \
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ENTRY(YMM6) \
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ENTRY(YMM7) \
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ENTRY(YMM8) \
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ENTRY(YMM9) \
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ENTRY(YMM10) \
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ENTRY(YMM11) \
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ENTRY(YMM12) \
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ENTRY(YMM13) \
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ENTRY(YMM14) \
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ENTRY(YMM15) \
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ENTRY(YMM16) \
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ENTRY(YMM17) \
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ENTRY(YMM18) \
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ENTRY(YMM19) \
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ENTRY(YMM20) \
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ENTRY(YMM21) \
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ENTRY(YMM22) \
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ENTRY(YMM23) \
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ENTRY(YMM24) \
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ENTRY(YMM25) \
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ENTRY(YMM26) \
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ENTRY(YMM27) \
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ENTRY(YMM28) \
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ENTRY(YMM29) \
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ENTRY(YMM30) \
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ENTRY(YMM31)
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#define REGS_ZMM \
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ENTRY(ZMM0) \
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ENTRY(ZMM1) \
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ENTRY(ZMM2) \
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ENTRY(ZMM3) \
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ENTRY(ZMM4) \
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ENTRY(ZMM5) \
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ENTRY(ZMM6) \
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ENTRY(ZMM7) \
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ENTRY(ZMM8) \
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ENTRY(ZMM9) \
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ENTRY(ZMM10) \
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ENTRY(ZMM11) \
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ENTRY(ZMM12) \
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ENTRY(ZMM13) \
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ENTRY(ZMM14) \
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ENTRY(ZMM15) \
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ENTRY(ZMM16) \
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ENTRY(ZMM17) \
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ENTRY(ZMM18) \
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ENTRY(ZMM19) \
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ENTRY(ZMM20) \
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ENTRY(ZMM21) \
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ENTRY(ZMM22) \
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ENTRY(ZMM23) \
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ENTRY(ZMM24) \
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ENTRY(ZMM25) \
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ENTRY(ZMM26) \
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ENTRY(ZMM27) \
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ENTRY(ZMM28) \
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ENTRY(ZMM29) \
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ENTRY(ZMM30) \
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ENTRY(ZMM31)
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#define REGS_MASKS \
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ENTRY(K0) \
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ENTRY(K1) \
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ENTRY(K2) \
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ENTRY(K3) \
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ENTRY(K4) \
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ENTRY(K5) \
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ENTRY(K6) \
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ENTRY(K7)
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#define REGS_MASK_PAIRS \
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ENTRY(K0_K1) \
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ENTRY(K2_K3) \
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ENTRY(K4_K5) \
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ENTRY(K6_K7)
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#define REGS_SEGMENT \
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ENTRY(ES) \
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ENTRY(CS) \
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ENTRY(SS) \
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ENTRY(DS) \
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ENTRY(FS) \
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ENTRY(GS)
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#define REGS_DEBUG \
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ENTRY(DR0) \
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ENTRY(DR1) \
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ENTRY(DR2) \
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ENTRY(DR3) \
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ENTRY(DR4) \
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ENTRY(DR5) \
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ENTRY(DR6) \
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ENTRY(DR7) \
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ENTRY(DR8) \
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ENTRY(DR9) \
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ENTRY(DR10) \
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ENTRY(DR11) \
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ENTRY(DR12) \
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ENTRY(DR13) \
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ENTRY(DR14) \
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ENTRY(DR15)
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#define REGS_CONTROL \
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ENTRY(CR0) \
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ENTRY(CR1) \
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ENTRY(CR2) \
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ENTRY(CR3) \
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ENTRY(CR4) \
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ENTRY(CR5) \
|
||
|
|
ENTRY(CR6) \
|
||
|
|
ENTRY(CR7) \
|
||
|
|
ENTRY(CR8) \
|
||
|
|
ENTRY(CR9) \
|
||
|
|
ENTRY(CR10) \
|
||
|
|
ENTRY(CR11) \
|
||
|
|
ENTRY(CR12) \
|
||
|
|
ENTRY(CR13) \
|
||
|
|
ENTRY(CR14) \
|
||
|
|
ENTRY(CR15)
|
||
|
|
|
||
|
|
#define REGS_BOUND \
|
||
|
|
ENTRY(BND0) \
|
||
|
|
ENTRY(BND1) \
|
||
|
|
ENTRY(BND2) \
|
||
|
|
ENTRY(BND3)
|
||
|
|
|
||
|
|
#undef REGS_TMM
|
||
|
|
#define REGS_TMM \
|
||
|
|
ENTRY(TMM0) \
|
||
|
|
ENTRY(TMM1) \
|
||
|
|
ENTRY(TMM2) \
|
||
|
|
ENTRY(TMM3) \
|
||
|
|
ENTRY(TMM4) \
|
||
|
|
ENTRY(TMM5) \
|
||
|
|
ENTRY(TMM6) \
|
||
|
|
ENTRY(TMM7)
|
||
|
|
|
||
|
|
#define ALL_EA_BASES \
|
||
|
|
EA_BASES_16BIT \
|
||
|
|
EA_BASES_32BIT \
|
||
|
|
EA_BASES_64BIT
|
||
|
|
|
||
|
|
#define ALL_SIB_BASES \
|
||
|
|
REGS_32BIT \
|
||
|
|
REGS_64BIT
|
||
|
|
|
||
|
|
#define ALL_REGS \
|
||
|
|
REGS_8BIT \
|
||
|
|
REGS_16BIT \
|
||
|
|
REGS_32BIT \
|
||
|
|
REGS_64BIT \
|
||
|
|
REGS_MMX \
|
||
|
|
REGS_XMM \
|
||
|
|
REGS_YMM \
|
||
|
|
REGS_ZMM \
|
||
|
|
REGS_MASKS \
|
||
|
|
REGS_MASK_PAIRS \
|
||
|
|
REGS_SEGMENT \
|
||
|
|
REGS_DEBUG \
|
||
|
|
REGS_CONTROL \
|
||
|
|
REGS_BOUND \
|
||
|
|
REGS_TMM \
|
||
|
|
ENTRY(RIP)
|
||
|
|
|
||
|
|
/// All possible values of the base field for effective-address
|
||
|
|
/// computations, a.k.a. the Mod and R/M fields of the ModR/M byte.
|
||
|
|
/// We distinguish between bases (EA_BASE_*) and registers that just happen
|
||
|
|
/// to be referred to when Mod == 0b11 (EA_REG_*).
|
||
|
|
enum EABase {
|
||
|
|
EA_BASE_NONE,
|
||
|
|
#define ENTRY(x) EA_BASE_##x,
|
||
|
|
ALL_EA_BASES
|
||
|
|
#undef ENTRY
|
||
|
|
#define ENTRY(x) EA_REG_##x,
|
||
|
|
ALL_REGS
|
||
|
|
#undef ENTRY
|
||
|
|
EA_max
|
||
|
|
};
|
||
|
|
|
||
|
|
/// All possible values of the SIB index field.
|
||
|
|
/// borrows entries from ALL_EA_BASES with the special case that
|
||
|
|
/// sib is synonymous with NONE.
|
||
|
|
/// Vector SIB: index can be XMM or YMM.
|
||
|
|
enum SIBIndex {
|
||
|
|
SIB_INDEX_NONE,
|
||
|
|
#define ENTRY(x) SIB_INDEX_##x,
|
||
|
|
ALL_EA_BASES
|
||
|
|
REGS_XMM
|
||
|
|
REGS_YMM
|
||
|
|
REGS_ZMM
|
||
|
|
#undef ENTRY
|
||
|
|
SIB_INDEX_max
|
||
|
|
};
|
||
|
|
|
||
|
|
/// All possible values of the SIB base field.
|
||
|
|
enum SIBBase {
|
||
|
|
SIB_BASE_NONE,
|
||
|
|
#define ENTRY(x) SIB_BASE_##x,
|
||
|
|
ALL_SIB_BASES
|
||
|
|
#undef ENTRY
|
||
|
|
SIB_BASE_max
|
||
|
|
};
|
||
|
|
|
||
|
|
/// Possible displacement types for effective-address computations.
|
||
|
|
enum EADisplacement {
|
||
|
|
EA_DISP_NONE,
|
||
|
|
EA_DISP_8,
|
||
|
|
EA_DISP_16,
|
||
|
|
EA_DISP_32
|
||
|
|
};
|
||
|
|
|
||
|
|
/// All possible values of the reg field in the ModR/M byte.
|
||
|
|
enum Reg {
|
||
|
|
#define ENTRY(x) MODRM_REG_##x,
|
||
|
|
ALL_REGS
|
||
|
|
#undef ENTRY
|
||
|
|
MODRM_REG_max
|
||
|
|
};
|
||
|
|
|
||
|
|
/// All possible segment overrides.
|
||
|
|
enum SegmentOverride {
|
||
|
|
SEG_OVERRIDE_NONE,
|
||
|
|
SEG_OVERRIDE_CS,
|
||
|
|
SEG_OVERRIDE_SS,
|
||
|
|
SEG_OVERRIDE_DS,
|
||
|
|
SEG_OVERRIDE_ES,
|
||
|
|
SEG_OVERRIDE_FS,
|
||
|
|
SEG_OVERRIDE_GS,
|
||
|
|
SEG_OVERRIDE_max
|
||
|
|
};
|
||
|
|
|
||
|
|
/// Possible values for the VEX.m-mmmm field
|
||
|
|
enum VEXLeadingOpcodeByte {
|
||
|
|
VEX_LOB_0F = 0x1,
|
||
|
|
VEX_LOB_0F38 = 0x2,
|
||
|
|
VEX_LOB_0F3A = 0x3
|
||
|
|
};
|
||
|
|
|
||
|
|
enum XOPMapSelect {
|
||
|
|
XOP_MAP_SELECT_8 = 0x8,
|
||
|
|
XOP_MAP_SELECT_9 = 0x9,
|
||
|
|
XOP_MAP_SELECT_A = 0xA
|
||
|
|
};
|
||
|
|
|
||
|
|
/// Possible values for the VEX.pp/EVEX.pp field
|
||
|
|
enum VEXPrefixCode {
|
||
|
|
VEX_PREFIX_NONE = 0x0,
|
||
|
|
VEX_PREFIX_66 = 0x1,
|
||
|
|
VEX_PREFIX_F3 = 0x2,
|
||
|
|
VEX_PREFIX_F2 = 0x3
|
||
|
|
};
|
||
|
|
|
||
|
|
enum VectorExtensionType {
|
||
|
|
TYPE_NO_VEX_XOP = 0x0,
|
||
|
|
TYPE_VEX_2B = 0x1,
|
||
|
|
TYPE_VEX_3B = 0x2,
|
||
|
|
TYPE_EVEX = 0x3,
|
||
|
|
TYPE_XOP = 0x4
|
||
|
|
};
|
||
|
|
|
||
|
|
/// The specification for how to extract and interpret a full instruction and
|
||
|
|
/// its operands.
|
||
|
|
struct InstructionSpecifier {
|
||
|
|
uint16_t operands;
|
||
|
|
};
|
||
|
|
|
||
|
|
/// The x86 internal instruction, which is produced by the decoder.
|
||
|
|
struct InternalInstruction {
|
||
|
|
// Opaque value passed to the reader
|
||
|
|
llvm::ArrayRef<uint8_t> bytes;
|
||
|
|
// The address of the next byte to read via the reader
|
||
|
|
uint64_t readerCursor;
|
||
|
|
|
||
|
|
// General instruction information
|
||
|
|
|
||
|
|
// The mode to disassemble for (64-bit, protected, real)
|
||
|
|
DisassemblerMode mode;
|
||
|
|
// The start of the instruction, usable with the reader
|
||
|
|
uint64_t startLocation;
|
||
|
|
// The length of the instruction, in bytes
|
||
|
|
size_t length;
|
||
|
|
|
||
|
|
// Prefix state
|
||
|
|
|
||
|
|
// The possible mandatory prefix
|
||
|
|
uint8_t mandatoryPrefix;
|
||
|
|
// The value of the vector extension prefix(EVEX/VEX/XOP), if present
|
||
|
|
uint8_t vectorExtensionPrefix[4];
|
||
|
|
// The type of the vector extension prefix
|
||
|
|
VectorExtensionType vectorExtensionType;
|
||
|
|
// The value of the REX prefix, if present
|
||
|
|
uint8_t rexPrefix;
|
||
|
|
// The segment override type
|
||
|
|
SegmentOverride segmentOverride;
|
||
|
|
// 1 if the prefix byte, 0xf2 or 0xf3 is xacquire or xrelease
|
||
|
|
bool xAcquireRelease;
|
||
|
|
|
||
|
|
// Address-size override
|
||
|
|
bool hasAdSize;
|
||
|
|
// Operand-size override
|
||
|
|
bool hasOpSize;
|
||
|
|
// Lock prefix
|
||
|
|
bool hasLockPrefix;
|
||
|
|
// The repeat prefix if any
|
||
|
|
uint8_t repeatPrefix;
|
||
|
|
|
||
|
|
// Sizes of various critical pieces of data, in bytes
|
||
|
|
uint8_t registerSize;
|
||
|
|
uint8_t addressSize;
|
||
|
|
uint8_t displacementSize;
|
||
|
|
uint8_t immediateSize;
|
||
|
|
|
||
|
|
// Offsets from the start of the instruction to the pieces of data, which is
|
||
|
|
// needed to find relocation entries for adding symbolic operands.
|
||
|
|
uint8_t displacementOffset;
|
||
|
|
uint8_t immediateOffset;
|
||
|
|
|
||
|
|
// opcode state
|
||
|
|
|
||
|
|
// The last byte of the opcode, not counting any ModR/M extension
|
||
|
|
uint8_t opcode;
|
||
|
|
|
||
|
|
// decode state
|
||
|
|
|
||
|
|
// The type of opcode, used for indexing into the array of decode tables
|
||
|
|
OpcodeType opcodeType;
|
||
|
|
// The instruction ID, extracted from the decode table
|
||
|
|
uint16_t instructionID;
|
||
|
|
// The specifier for the instruction, from the instruction info table
|
||
|
|
const InstructionSpecifier *spec;
|
||
|
|
|
||
|
|
// state for additional bytes, consumed during operand decode. Pattern:
|
||
|
|
// consumed___ indicates that the byte was already consumed and does not
|
||
|
|
// need to be consumed again.
|
||
|
|
|
||
|
|
// The VEX.vvvv field, which contains a third register operand for some AVX
|
||
|
|
// instructions.
|
||
|
|
Reg vvvv;
|
||
|
|
|
||
|
|
// The writemask for AVX-512 instructions which is contained in EVEX.aaa
|
||
|
|
Reg writemask;
|
||
|
|
|
||
|
|
// The ModR/M byte, which contains most register operands and some portion of
|
||
|
|
// all memory operands.
|
||
|
|
bool consumedModRM;
|
||
|
|
uint8_t modRM;
|
||
|
|
|
||
|
|
// The SIB byte, used for more complex 32- or 64-bit memory operands
|
||
|
|
uint8_t sib;
|
||
|
|
|
||
|
|
// The displacement, used for memory operands
|
||
|
|
int32_t displacement;
|
||
|
|
|
||
|
|
// Immediates. There can be two in some cases
|
||
|
|
uint8_t numImmediatesConsumed;
|
||
|
|
uint8_t numImmediatesTranslated;
|
||
|
|
uint64_t immediates[2];
|
||
|
|
|
||
|
|
// A register or immediate operand encoded into the opcode
|
||
|
|
Reg opcodeRegister;
|
||
|
|
|
||
|
|
// Portions of the ModR/M byte
|
||
|
|
|
||
|
|
// These fields determine the allowable values for the ModR/M fields, which
|
||
|
|
// depend on operand and address widths.
|
||
|
|
EABase eaRegBase;
|
||
|
|
Reg regBase;
|
||
|
|
|
||
|
|
// The Mod and R/M fields can encode a base for an effective address, or a
|
||
|
|
// register. These are separated into two fields here.
|
||
|
|
EABase eaBase;
|
||
|
|
EADisplacement eaDisplacement;
|
||
|
|
// The reg field always encodes a register
|
||
|
|
Reg reg;
|
||
|
|
|
||
|
|
// SIB state
|
||
|
|
SIBIndex sibIndexBase;
|
||
|
|
SIBIndex sibIndex;
|
||
|
|
uint8_t sibScale;
|
||
|
|
SIBBase sibBase;
|
||
|
|
|
||
|
|
// Embedded rounding control.
|
||
|
|
uint8_t RC;
|
||
|
|
|
||
|
|
ArrayRef<OperandSpecifier> operands;
|
||
|
|
};
|
||
|
|
|
||
|
|
} // namespace X86Disassembler
|
||
|
|
} // namespace llvm
|
||
|
|
|
||
|
|
#endif
|