288 lines
11 KiB
C++
288 lines
11 KiB
C++
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//===----- RISCVMergeBaseOffset.cpp - Optimise address calculations ------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Merge the offset of address calculation into the offset field
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// of instructions in a global address lowering sequence. This pass transforms:
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// lui vreg1, %hi(s)
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// addi vreg2, vreg1, %lo(s)
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// addi vreg3, verg2, Offset
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//
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// Into:
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// lui vreg1, %hi(s+Offset)
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// addi vreg2, vreg1, %lo(s+Offset)
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//
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// The transformation is carried out under certain conditions:
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// 1) The offset field in the base of global address lowering sequence is zero.
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// 2) The lowered global address has only one use.
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//
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// The offset field can be in a different form. This pass handles all of them.
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//===----------------------------------------------------------------------===//
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#include "RISCV.h"
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#include "RISCVTargetMachine.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetOptions.h"
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#include <set>
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using namespace llvm;
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#define DEBUG_TYPE "riscv-merge-base-offset"
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#define RISCV_MERGE_BASE_OFFSET_NAME "RISCV Merge Base Offset"
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namespace {
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struct RISCVMergeBaseOffsetOpt : public MachineFunctionPass {
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static char ID;
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const MachineFunction *MF;
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bool runOnMachineFunction(MachineFunction &Fn) override;
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bool detectLuiAddiGlobal(MachineInstr &LUI, MachineInstr *&ADDI);
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bool detectAndFoldOffset(MachineInstr &HiLUI, MachineInstr &LoADDI);
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void foldOffset(MachineInstr &HiLUI, MachineInstr &LoADDI, MachineInstr &Tail,
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int64_t Offset);
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bool matchLargeOffset(MachineInstr &TailAdd, Register GSReg, int64_t &Offset);
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RISCVMergeBaseOffsetOpt() : MachineFunctionPass(ID) {}
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::IsSSA);
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}
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StringRef getPassName() const override {
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return RISCV_MERGE_BASE_OFFSET_NAME;
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}
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private:
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MachineRegisterInfo *MRI;
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std::set<MachineInstr *> DeadInstrs;
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};
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} // end anonymous namespace
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char RISCVMergeBaseOffsetOpt::ID = 0;
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INITIALIZE_PASS(RISCVMergeBaseOffsetOpt, DEBUG_TYPE,
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RISCV_MERGE_BASE_OFFSET_NAME, false, false)
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// Detect the pattern:
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// lui vreg1, %hi(s)
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// addi vreg2, vreg1, %lo(s)
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//
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// Pattern only accepted if:
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// 1) ADDI has only one use.
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// 2) LUI has only one use; which is the ADDI.
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// 3) Both ADDI and LUI have GlobalAddress type which indicates that these
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// are generated from global address lowering.
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// 4) Offset value in the Global Address is 0.
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bool RISCVMergeBaseOffsetOpt::detectLuiAddiGlobal(MachineInstr &HiLUI,
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MachineInstr *&LoADDI) {
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if (HiLUI.getOpcode() != RISCV::LUI ||
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HiLUI.getOperand(1).getTargetFlags() != RISCVII::MO_HI ||
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HiLUI.getOperand(1).getType() != MachineOperand::MO_GlobalAddress ||
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HiLUI.getOperand(1).getOffset() != 0 ||
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!MRI->hasOneUse(HiLUI.getOperand(0).getReg()))
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return false;
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Register HiLuiDestReg = HiLUI.getOperand(0).getReg();
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LoADDI = MRI->use_begin(HiLuiDestReg)->getParent();
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if (LoADDI->getOpcode() != RISCV::ADDI ||
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LoADDI->getOperand(2).getTargetFlags() != RISCVII::MO_LO ||
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LoADDI->getOperand(2).getType() != MachineOperand::MO_GlobalAddress ||
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LoADDI->getOperand(2).getOffset() != 0 ||
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!MRI->hasOneUse(LoADDI->getOperand(0).getReg()))
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return false;
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return true;
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}
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// Update the offset in HiLUI and LoADDI instructions.
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// Delete the tail instruction and update all the uses to use the
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// output from LoADDI.
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void RISCVMergeBaseOffsetOpt::foldOffset(MachineInstr &HiLUI,
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MachineInstr &LoADDI,
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MachineInstr &Tail, int64_t Offset) {
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// Put the offset back in HiLUI and the LoADDI
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HiLUI.getOperand(1).setOffset(Offset);
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LoADDI.getOperand(2).setOffset(Offset);
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// Delete the tail instruction.
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DeadInstrs.insert(&Tail);
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MRI->replaceRegWith(Tail.getOperand(0).getReg(),
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LoADDI.getOperand(0).getReg());
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LLVM_DEBUG(dbgs() << " Merged offset " << Offset << " into base.\n"
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<< " " << HiLUI << " " << LoADDI;);
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}
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// Detect patterns for large offsets that are passed into an ADD instruction.
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//
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// Base address lowering is of the form:
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// HiLUI: lui vreg1, %hi(s)
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// LoADDI: addi vreg2, vreg1, %lo(s)
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// / \
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// / \
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// / \
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// / The large offset can be of two forms: \
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// 1) Offset that has non zero bits in lower 2) Offset that has non zero
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// 12 bits and upper 20 bits bits in upper 20 bits only
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// OffseLUI: lui vreg3, 4
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// OffsetTail: addi voff, vreg3, 188 OffsetTail: lui voff, 128
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// \ /
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// \ /
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// \ /
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// \ /
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// TailAdd: add vreg4, vreg2, voff
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bool RISCVMergeBaseOffsetOpt::matchLargeOffset(MachineInstr &TailAdd,
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Register GAReg,
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int64_t &Offset) {
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assert((TailAdd.getOpcode() == RISCV::ADD) && "Expected ADD instruction!");
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Register Rs = TailAdd.getOperand(1).getReg();
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Register Rt = TailAdd.getOperand(2).getReg();
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Register Reg = Rs == GAReg ? Rt : Rs;
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// Can't fold if the register has more than one use.
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if (!MRI->hasOneUse(Reg))
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return false;
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// This can point to an ADDI or a LUI:
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MachineInstr &OffsetTail = *MRI->getVRegDef(Reg);
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if (OffsetTail.getOpcode() == RISCV::ADDI) {
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// The offset value has non zero bits in both %hi and %lo parts.
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// Detect an ADDI that feeds from a LUI instruction.
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MachineOperand &AddiImmOp = OffsetTail.getOperand(2);
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if (AddiImmOp.getTargetFlags() != RISCVII::MO_None)
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return false;
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int64_t OffLo = AddiImmOp.getImm();
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MachineInstr &OffsetLui =
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*MRI->getVRegDef(OffsetTail.getOperand(1).getReg());
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MachineOperand &LuiImmOp = OffsetLui.getOperand(1);
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if (OffsetLui.getOpcode() != RISCV::LUI ||
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LuiImmOp.getTargetFlags() != RISCVII::MO_None ||
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!MRI->hasOneUse(OffsetLui.getOperand(0).getReg()))
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return false;
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int64_t OffHi = OffsetLui.getOperand(1).getImm();
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Offset = (OffHi << 12) + OffLo;
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LLVM_DEBUG(dbgs() << " Offset Instrs: " << OffsetTail
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<< " " << OffsetLui);
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DeadInstrs.insert(&OffsetTail);
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DeadInstrs.insert(&OffsetLui);
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return true;
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} else if (OffsetTail.getOpcode() == RISCV::LUI) {
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// The offset value has all zero bits in the lower 12 bits. Only LUI
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// exists.
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LLVM_DEBUG(dbgs() << " Offset Instr: " << OffsetTail);
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Offset = OffsetTail.getOperand(1).getImm() << 12;
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DeadInstrs.insert(&OffsetTail);
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return true;
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}
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return false;
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}
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bool RISCVMergeBaseOffsetOpt::detectAndFoldOffset(MachineInstr &HiLUI,
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MachineInstr &LoADDI) {
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Register DestReg = LoADDI.getOperand(0).getReg();
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assert(MRI->hasOneUse(DestReg) && "expected one use for LoADDI");
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// LoADDI has only one use.
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MachineInstr &Tail = *MRI->use_begin(DestReg)->getParent();
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switch (Tail.getOpcode()) {
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default:
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LLVM_DEBUG(dbgs() << "Don't know how to get offset from this instr:"
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<< Tail);
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return false;
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case RISCV::ADDI: {
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// Offset is simply an immediate operand.
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int64_t Offset = Tail.getOperand(2).getImm();
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LLVM_DEBUG(dbgs() << " Offset Instr: " << Tail);
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foldOffset(HiLUI, LoADDI, Tail, Offset);
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return true;
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} break;
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case RISCV::ADD: {
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// The offset is too large to fit in the immediate field of ADDI.
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// This can be in two forms:
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// 1) LUI hi_Offset followed by:
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// ADDI lo_offset
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// This happens in case the offset has non zero bits in
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// both hi 20 and lo 12 bits.
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// 2) LUI (offset20)
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// This happens in case the lower 12 bits of the offset are zeros.
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int64_t Offset;
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if (!matchLargeOffset(Tail, DestReg, Offset))
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return false;
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foldOffset(HiLUI, LoADDI, Tail, Offset);
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return true;
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} break;
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case RISCV::LB:
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case RISCV::LH:
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case RISCV::LW:
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case RISCV::LBU:
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case RISCV::LHU:
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case RISCV::LWU:
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case RISCV::LD:
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case RISCV::FLH:
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case RISCV::FLW:
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case RISCV::FLD:
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case RISCV::SB:
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case RISCV::SH:
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case RISCV::SW:
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case RISCV::SD:
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case RISCV::FSH:
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case RISCV::FSW:
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case RISCV::FSD: {
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// Transforms the sequence: Into:
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// HiLUI: lui vreg1, %hi(foo) ---> lui vreg1, %hi(foo+8)
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// LoADDI: addi vreg2, vreg1, %lo(foo) ---> lw vreg3, lo(foo+8)(vreg1)
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// Tail: lw vreg3, 8(vreg2)
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if (Tail.getOperand(1).isFI())
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return false;
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// Register defined by LoADDI should be used in the base part of the
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// load\store instruction. Otherwise, no folding possible.
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Register BaseAddrReg = Tail.getOperand(1).getReg();
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if (DestReg != BaseAddrReg)
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return false;
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MachineOperand &TailImmOp = Tail.getOperand(2);
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int64_t Offset = TailImmOp.getImm();
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// Update the offsets in global address lowering.
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HiLUI.getOperand(1).setOffset(Offset);
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// Update the immediate in the Tail instruction to add the offset.
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Tail.RemoveOperand(2);
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MachineOperand &ImmOp = LoADDI.getOperand(2);
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ImmOp.setOffset(Offset);
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Tail.addOperand(ImmOp);
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// Update the base reg in the Tail instruction to feed from LUI.
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// Output of HiLUI is only used in LoADDI, no need to use
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// MRI->replaceRegWith().
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Tail.getOperand(1).setReg(HiLUI.getOperand(0).getReg());
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DeadInstrs.insert(&LoADDI);
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return true;
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} break;
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}
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return false;
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}
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bool RISCVMergeBaseOffsetOpt::runOnMachineFunction(MachineFunction &Fn) {
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if (skipFunction(Fn.getFunction()))
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return false;
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DeadInstrs.clear();
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MRI = &Fn.getRegInfo();
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for (MachineBasicBlock &MBB : Fn) {
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LLVM_DEBUG(dbgs() << "MBB: " << MBB.getName() << "\n");
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for (MachineInstr &HiLUI : MBB) {
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MachineInstr *LoADDI = nullptr;
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if (!detectLuiAddiGlobal(HiLUI, LoADDI))
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continue;
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LLVM_DEBUG(dbgs() << " Found lowered global address with one use: "
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<< *LoADDI->getOperand(2).getGlobal() << "\n");
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// If the use count is only one, merge the offset
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detectAndFoldOffset(HiLUI, *LoADDI);
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}
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}
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// Delete dead instructions.
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for (auto *MI : DeadInstrs)
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MI->eraseFromParent();
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return true;
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}
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/// Returns an instance of the Merge Base Offset Optimization pass.
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FunctionPass *llvm::createRISCVMergeBaseOffsetOptPass() {
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return new RISCVMergeBaseOffsetOpt();
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}
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