644 lines
29 KiB
TableGen
644 lines
29 KiB
TableGen
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//===- RISCVInstrInfoVSDPatterns.td - RVV SDNode patterns --*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// This file contains the required infrastructure and SDNode patterns to
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/// support code generation for the standard 'V' (Vector) extension, version
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/// 0.10. This version is still experimental as the 'V' extension hasn't been
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/// ratified yet.
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///
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/// This file is included from and depends upon RISCVInstrInfoVPseudos.td
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///
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/// Note: the patterns for RVV intrinsics are found in
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/// RISCVInstrInfoVPseudos.td.
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///
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Helpers to define the SDNode patterns.
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//===----------------------------------------------------------------------===//
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def SDTSplatI64 : SDTypeProfile<1, 1, [
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SDTCVecEltisVT<0, i64>, SDTCisVT<1, i32>
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]>;
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def rv32_splat_i64 : SDNode<"RISCVISD::SPLAT_VECTOR_I64", SDTSplatI64>;
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def riscv_trunc_vector : SDNode<"RISCVISD::TRUNCATE_VECTOR",
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SDTypeProfile<1, 1,
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[SDTCisVec<0>, SDTCisVec<1>]>>;
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// Penalize the generic form with Complexity=1 to give the simm5/uimm5 variants
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// precedence
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def SplatPat : ComplexPattern<vAny, 1, "selectVSplat", [], [], 1>;
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def SplatPat_simm5 : ComplexPattern<vAny, 1, "selectVSplatSimm5", []>;
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def SplatPat_uimm5 : ComplexPattern<vAny, 1, "selectVSplatUimm5", []>;
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class SwapHelper<dag Prefix, dag A, dag B, dag Suffix, bit swap> {
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dag Value = !con(Prefix, !if(swap, B, A), !if(swap, A, B), Suffix);
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}
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multiclass VPatUSLoadStoreSDNode<LLVMType type,
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LLVMType mask_type,
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int sew,
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LMULInfo vlmul,
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OutPatFrag avl,
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RegisterClass reg_rs1,
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VReg reg_class>
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{
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defvar load_instr = !cast<Instruction>("PseudoVLE"#sew#"_V_"#vlmul.MX);
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defvar store_instr = !cast<Instruction>("PseudoVSE"#sew#"_V_"#vlmul.MX);
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// Load
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def : Pat<(type (load reg_rs1:$rs1)),
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(load_instr reg_rs1:$rs1, avl, sew)>;
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// Store
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def : Pat<(store type:$rs2, reg_rs1:$rs1),
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(store_instr reg_class:$rs2, reg_rs1:$rs1, avl, sew)>;
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}
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multiclass VPatUSLoadStoreSDNodes<RegisterClass reg_rs1> {
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foreach vti = AllVectors in
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defm "" : VPatUSLoadStoreSDNode<vti.Vector, vti.Mask, vti.SEW, vti.LMul,
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vti.AVL, reg_rs1, vti.RegClass>;
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}
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class VPatBinarySDNode_VV<SDNode vop,
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string instruction_name,
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ValueType result_type,
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ValueType op_type,
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ValueType mask_type,
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int sew,
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LMULInfo vlmul,
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OutPatFrag avl,
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VReg RetClass,
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VReg op_reg_class> :
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Pat<(result_type (vop
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(op_type op_reg_class:$rs1),
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(op_type op_reg_class:$rs2))),
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(!cast<Instruction>(instruction_name#"_VV_"# vlmul.MX)
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op_reg_class:$rs1,
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op_reg_class:$rs2,
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avl, sew)>;
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class VPatBinarySDNode_XI<SDNode vop,
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string instruction_name,
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string suffix,
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ValueType result_type,
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ValueType vop_type,
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ValueType xop_type,
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ValueType mask_type,
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int sew,
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LMULInfo vlmul,
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OutPatFrag avl,
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VReg RetClass,
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VReg vop_reg_class,
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ComplexPattern SplatPatKind,
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DAGOperand xop_kind> :
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Pat<(result_type (vop
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(vop_type vop_reg_class:$rs1),
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(vop_type (SplatPatKind xop_kind:$rs2)))),
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(!cast<Instruction>(instruction_name#_#suffix#_# vlmul.MX)
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vop_reg_class:$rs1,
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xop_kind:$rs2,
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avl, sew)>;
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multiclass VPatBinarySDNode_VV_VX<SDNode vop, string instruction_name>
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{
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foreach vti = AllIntegerVectors in {
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def : VPatBinarySDNode_VV<vop, instruction_name,
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vti.Vector, vti.Vector, vti.Mask, vti.SEW,
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vti.LMul, vti.AVL, vti.RegClass, vti.RegClass>;
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def : VPatBinarySDNode_XI<vop, instruction_name, "VX",
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vti.Vector, vti.Vector, XLenVT, vti.Mask, vti.SEW,
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vti.LMul, vti.AVL, vti.RegClass, vti.RegClass,
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SplatPat, GPR>;
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}
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}
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multiclass VPatBinarySDNode_VV_VX_VI<SDNode vop, string instruction_name,
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Operand ImmType = simm5>
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{
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foreach vti = AllIntegerVectors in {
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def : VPatBinarySDNode_VV<vop, instruction_name,
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vti.Vector, vti.Vector, vti.Mask, vti.SEW,
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vti.LMul, vti.AVL, vti.RegClass, vti.RegClass>;
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def : VPatBinarySDNode_XI<vop, instruction_name, "VX",
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vti.Vector, vti.Vector, XLenVT, vti.Mask, vti.SEW,
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vti.LMul, vti.AVL, vti.RegClass, vti.RegClass,
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SplatPat, GPR>;
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def : VPatBinarySDNode_XI<vop, instruction_name, "VI",
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vti.Vector, vti.Vector, XLenVT, vti.Mask, vti.SEW,
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vti.LMul, vti.AVL, vti.RegClass, vti.RegClass,
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!cast<ComplexPattern>(SplatPat#_#ImmType),
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ImmType>;
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}
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}
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class VPatBinarySDNode_VF<SDNode vop,
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string instruction_name,
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ValueType result_type,
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ValueType vop_type,
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ValueType xop_type,
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ValueType mask_type,
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int sew,
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LMULInfo vlmul,
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OutPatFrag avl,
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VReg RetClass,
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VReg vop_reg_class,
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DAGOperand xop_kind> :
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Pat<(result_type (vop (vop_type vop_reg_class:$rs1),
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(vop_type (splat_vector xop_kind:$rs2)))),
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(!cast<Instruction>(instruction_name#"_"#vlmul.MX)
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vop_reg_class:$rs1,
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(xop_type xop_kind:$rs2),
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avl, sew)>;
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multiclass VPatBinaryFPSDNode_VV_VF<SDNode vop, string instruction_name> {
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foreach vti = AllFloatVectors in {
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def : VPatBinarySDNode_VV<vop, instruction_name,
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vti.Vector, vti.Vector, vti.Mask, vti.SEW,
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vti.LMul, vti.AVL, vti.RegClass, vti.RegClass>;
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def : VPatBinarySDNode_VF<vop, instruction_name#"_V"#vti.ScalarSuffix,
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vti.Vector, vti.Vector, vti.Scalar, vti.Mask,
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vti.SEW, vti.LMul, vti.AVL, vti.RegClass, vti.RegClass,
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vti.ScalarRegClass>;
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}
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}
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multiclass VPatBinaryFPSDNode_R_VF<SDNode vop, string instruction_name> {
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foreach fvti = AllFloatVectors in
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def : Pat<(fvti.Vector (vop (fvti.Vector (splat_vector fvti.Scalar:$rs2)),
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(fvti.Vector fvti.RegClass:$rs1))),
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(!cast<Instruction>(instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX)
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fvti.RegClass:$rs1,
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(fvti.Scalar fvti.ScalarRegClass:$rs2),
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fvti.AVL, fvti.SEW)>;
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}
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multiclass VPatIntegerSetCCSDNode_VV<CondCode cc,
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string instruction_name,
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bit swap = 0> {
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foreach vti = AllIntegerVectors in {
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defvar instruction = !cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX);
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def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1),
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(vti.Vector vti.RegClass:$rs2), cc)),
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SwapHelper<(instruction),
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(instruction vti.RegClass:$rs1),
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(instruction vti.RegClass:$rs2),
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(instruction vti.AVL, vti.SEW),
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swap>.Value>;
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}
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}
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multiclass VPatIntegerSetCCSDNode_XI<CondCode cc,
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string instruction_name,
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string kind,
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ComplexPattern SplatPatKind,
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DAGOperand xop_kind,
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bit swap = 0> {
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foreach vti = AllIntegerVectors in {
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defvar instruction = !cast<Instruction>(instruction_name#_#kind#_#vti.LMul.MX);
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def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1),
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(vti.Vector (SplatPatKind xop_kind:$rs2)), cc)),
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SwapHelper<(instruction),
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(instruction vti.RegClass:$rs1),
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(instruction xop_kind:$rs2),
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(instruction vti.AVL, vti.SEW),
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swap>.Value>;
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}
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}
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multiclass VPatIntegerSetCCSDNode_VV_VX_VI<CondCode cc,
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string instruction_name,
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bit swap = 0> {
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defm : VPatIntegerSetCCSDNode_VV<cc, instruction_name, swap>;
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defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VX",
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SplatPat, GPR, swap>;
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defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VI",
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SplatPat_simm5, simm5, swap>;
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}
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multiclass VPatIntegerSetCCSDNode_VV_VX<CondCode cc,
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string instruction_name,
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bit swap = 0> {
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defm : VPatIntegerSetCCSDNode_VV<cc, instruction_name, swap>;
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defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VX",
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SplatPat, GPR, swap>;
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}
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multiclass VPatIntegerSetCCSDNode_VX_VI<CondCode cc,
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string instruction_name,
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bit swap = 0> {
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defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VX",
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SplatPat, GPR, swap>;
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defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VI",
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SplatPat_simm5, simm5, swap>;
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}
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multiclass VPatFPSetCCSDNode_VV<CondCode cc, string instruction_name> {
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foreach fvti = AllFloatVectors in
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def : Pat<(fvti.Mask (setcc (fvti.Vector fvti.RegClass:$rs1),
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(fvti.Vector fvti.RegClass:$rs2),
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cc)),
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(!cast<Instruction>(instruction_name#"_VV_"#fvti.LMul.MX)
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fvti.RegClass:$rs1, fvti.RegClass:$rs2, fvti.AVL, fvti.SEW)>;
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}
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multiclass VPatFPSetCCSDNode_VF<CondCode cc, string instruction_name> {
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foreach fvti = AllFloatVectors in
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def : Pat<(fvti.Mask (setcc (fvti.Vector fvti.RegClass:$rs1),
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(fvti.Vector (splat_vector fvti.ScalarRegClass:$rs2)),
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cc)),
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(!cast<Instruction>(instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX)
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fvti.RegClass:$rs1,
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(fvti.Scalar fvti.ScalarRegClass:$rs2),
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fvti.AVL, fvti.SEW)>;
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}
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multiclass VPatFPSetCCSDNode_FV<CondCode cc, string swapped_op_instruction_name> {
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foreach fvti = AllFloatVectors in
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def : Pat<(fvti.Mask (setcc (fvti.Vector (splat_vector fvti.ScalarRegClass:$rs2)),
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(fvti.Vector fvti.RegClass:$rs1),
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cc)),
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(!cast<Instruction>(swapped_op_instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX)
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fvti.RegClass:$rs1,
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(fvti.Scalar fvti.ScalarRegClass:$rs2),
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fvti.AVL, fvti.SEW)>;
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}
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multiclass VPatFPSetCCSDNode_VV_VF_FV<CondCode cc,
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string inst_name,
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string swapped_op_inst_name> {
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defm : VPatFPSetCCSDNode_VV<cc, inst_name>;
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defm : VPatFPSetCCSDNode_VF<cc, inst_name>;
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defm : VPatFPSetCCSDNode_FV<cc, swapped_op_inst_name>;
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}
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multiclass VPatExtendSDNode_V<list<SDNode> ops, string inst_name, string suffix,
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list <VTypeInfoToFraction> fraction_list> {
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foreach vtiTofti = fraction_list in {
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defvar vti = vtiTofti.Vti;
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defvar fti = vtiTofti.Fti;
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foreach op = ops in
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def : Pat<(vti.Vector (op (fti.Vector fti.RegClass:$rs2))),
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(!cast<Instruction>(inst_name#"_"#suffix#"_"#vti.LMul.MX)
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fti.RegClass:$rs2, fti.AVL, vti.SEW)>;
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}
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}
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//===----------------------------------------------------------------------===//
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// Patterns.
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtV] in {
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// 7.4. Vector Unit-Stride Instructions
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defm "" : VPatUSLoadStoreSDNodes<GPR>;
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defm "" : VPatUSLoadStoreSDNodes<AddrFI>;
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// 12.1. Vector Single-Width Integer Add and Subtract
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defm "" : VPatBinarySDNode_VV_VX_VI<add, "PseudoVADD">;
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defm "" : VPatBinarySDNode_VV_VX<sub, "PseudoVSUB">;
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// Handle VRSUB specially since it's the only integer binary op with reversed
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// pattern operands
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foreach vti = AllIntegerVectors in {
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def : Pat<(sub (vti.Vector (SplatPat XLenVT:$rs2)),
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(vti.Vector vti.RegClass:$rs1)),
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(!cast<Instruction>("PseudoVRSUB_VX_"# vti.LMul.MX)
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vti.RegClass:$rs1, GPR:$rs2, vti.AVL, vti.SEW)>;
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def : Pat<(sub (vti.Vector (SplatPat_simm5 XLenVT:$rs2)),
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(vti.Vector vti.RegClass:$rs1)),
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(!cast<Instruction>("PseudoVRSUB_VI_"# vti.LMul.MX)
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vti.RegClass:$rs1, simm5:$rs2, vti.AVL, vti.SEW)>;
|
||
|
|
}
|
||
|
|
|
||
|
|
// 12.3. Vector Integer Extension
|
||
|
|
defm "" : VPatExtendSDNode_V<[zext, anyext], "PseudoVZEXT", "VF2",
|
||
|
|
AllFractionableVF2IntVectors>;
|
||
|
|
defm "" : VPatExtendSDNode_V<[sext], "PseudoVSEXT", "VF2",
|
||
|
|
AllFractionableVF2IntVectors>;
|
||
|
|
defm "" : VPatExtendSDNode_V<[zext, anyext], "PseudoVZEXT", "VF4",
|
||
|
|
AllFractionableVF4IntVectors>;
|
||
|
|
defm "" : VPatExtendSDNode_V<[sext], "PseudoVSEXT", "VF4",
|
||
|
|
AllFractionableVF4IntVectors>;
|
||
|
|
defm "" : VPatExtendSDNode_V<[zext, anyext], "PseudoVZEXT", "VF8",
|
||
|
|
AllFractionableVF8IntVectors>;
|
||
|
|
defm "" : VPatExtendSDNode_V<[sext], "PseudoVSEXT", "VF8",
|
||
|
|
AllFractionableVF8IntVectors>;
|
||
|
|
|
||
|
|
// 12.5. Vector Bitwise Logical Instructions
|
||
|
|
defm "" : VPatBinarySDNode_VV_VX_VI<and, "PseudoVAND">;
|
||
|
|
defm "" : VPatBinarySDNode_VV_VX_VI<or, "PseudoVOR">;
|
||
|
|
defm "" : VPatBinarySDNode_VV_VX_VI<xor, "PseudoVXOR">;
|
||
|
|
|
||
|
|
// 12.6. Vector Single-Width Bit Shift Instructions
|
||
|
|
defm "" : VPatBinarySDNode_VV_VX_VI<shl, "PseudoVSLL", uimm5>;
|
||
|
|
defm "" : VPatBinarySDNode_VV_VX_VI<srl, "PseudoVSRL", uimm5>;
|
||
|
|
defm "" : VPatBinarySDNode_VV_VX_VI<sra, "PseudoVSRA", uimm5>;
|
||
|
|
|
||
|
|
// 12.7. Vector Narrowing Integer Right Shift Instructions
|
||
|
|
foreach vtiTofti = AllFractionableVF2IntVectors in {
|
||
|
|
defvar vti = vtiTofti.Vti;
|
||
|
|
defvar fti = vtiTofti.Fti;
|
||
|
|
def : Pat<(fti.Vector (riscv_trunc_vector (vti.Vector vti.RegClass:$rs1))),
|
||
|
|
(!cast<Instruction>("PseudoVNSRL_WI_"#fti.LMul.MX)
|
||
|
|
vti.RegClass:$rs1, 0, fti.AVL, fti.SEW)>;
|
||
|
|
}
|
||
|
|
|
||
|
|
// 12.8. Vector Integer Comparison Instructions
|
||
|
|
defm "" : VPatIntegerSetCCSDNode_VV_VX_VI<SETEQ, "PseudoVMSEQ">;
|
||
|
|
defm "" : VPatIntegerSetCCSDNode_VV_VX_VI<SETNE, "PseudoVMSNE">;
|
||
|
|
|
||
|
|
// FIXME: Support immediate forms of these by choosing SLE decrementing the
|
||
|
|
// immediate
|
||
|
|
defm "" : VPatIntegerSetCCSDNode_VV_VX<SETLT, "PseudoVMSLT">;
|
||
|
|
defm "" : VPatIntegerSetCCSDNode_VV_VX<SETULT, "PseudoVMSLTU">;
|
||
|
|
|
||
|
|
defm "" : VPatIntegerSetCCSDNode_VV<SETGT, "PseudoVMSLT", /*swap*/1>;
|
||
|
|
defm "" : VPatIntegerSetCCSDNode_VV<SETUGT, "PseudoVMSLTU", /*swap*/1>;
|
||
|
|
defm "" : VPatIntegerSetCCSDNode_VX_VI<SETGT, "PseudoVMSGT">;
|
||
|
|
defm "" : VPatIntegerSetCCSDNode_VX_VI<SETUGT, "PseudoVMSGTU">;
|
||
|
|
|
||
|
|
defm "" : VPatIntegerSetCCSDNode_VV_VX_VI<SETLE, "PseudoVMSLE">;
|
||
|
|
defm "" : VPatIntegerSetCCSDNode_VV_VX_VI<SETULE, "PseudoVMSLEU">;
|
||
|
|
|
||
|
|
// FIXME: Support immediate forms of these by choosing SGT and decrementing the
|
||
|
|
// immediate
|
||
|
|
defm "" : VPatIntegerSetCCSDNode_VV<SETGE, "PseudoVMSLE", /*swap*/1>;
|
||
|
|
defm "" : VPatIntegerSetCCSDNode_VV<SETUGE, "PseudoVMSLEU", /*swap*/1>;
|
||
|
|
|
||
|
|
// 12.9. Vector Integer Min/Max Instructions
|
||
|
|
defm "" : VPatBinarySDNode_VV_VX<umin, "PseudoVMINU">;
|
||
|
|
defm "" : VPatBinarySDNode_VV_VX<smin, "PseudoVMIN">;
|
||
|
|
defm "" : VPatBinarySDNode_VV_VX<umax, "PseudoVMAXU">;
|
||
|
|
defm "" : VPatBinarySDNode_VV_VX<smax, "PseudoVMAX">;
|
||
|
|
|
||
|
|
// 12.10. Vector Single-Width Integer Multiply Instructions
|
||
|
|
defm "" : VPatBinarySDNode_VV_VX<mul, "PseudoVMUL">;
|
||
|
|
defm "" : VPatBinarySDNode_VV_VX<mulhs, "PseudoVMULH">;
|
||
|
|
defm "" : VPatBinarySDNode_VV_VX<mulhu, "PseudoVMULHU">;
|
||
|
|
|
||
|
|
// 12.11. Vector Integer Divide Instructions
|
||
|
|
defm "" : VPatBinarySDNode_VV_VX<udiv, "PseudoVDIVU">;
|
||
|
|
defm "" : VPatBinarySDNode_VV_VX<sdiv, "PseudoVDIV">;
|
||
|
|
defm "" : VPatBinarySDNode_VV_VX<urem, "PseudoVREMU">;
|
||
|
|
defm "" : VPatBinarySDNode_VV_VX<srem, "PseudoVREM">;
|
||
|
|
|
||
|
|
// 12.16. Vector Integer Merge Instructions
|
||
|
|
foreach vti = AllIntegerVectors in {
|
||
|
|
def : Pat<(vti.Vector (vselect (vti.Mask VMV0:$vm), vti.RegClass:$rs1,
|
||
|
|
vti.RegClass:$rs2)),
|
||
|
|
(!cast<Instruction>("PseudoVMERGE_VVM_"#vti.LMul.MX)
|
||
|
|
vti.RegClass:$rs2, vti.RegClass:$rs1, VMV0:$vm,
|
||
|
|
vti.AVL, vti.SEW)>;
|
||
|
|
|
||
|
|
def : Pat<(vti.Vector (vselect (vti.Mask VMV0:$vm), (SplatPat XLenVT:$rs1),
|
||
|
|
vti.RegClass:$rs2)),
|
||
|
|
(!cast<Instruction>("PseudoVMERGE_VXM_"#vti.LMul.MX)
|
||
|
|
vti.RegClass:$rs2, GPR:$rs1, VMV0:$vm, vti.AVL, vti.SEW)>;
|
||
|
|
|
||
|
|
def : Pat<(vti.Vector (vselect (vti.Mask VMV0:$vm), (SplatPat_simm5 simm5:$rs1),
|
||
|
|
vti.RegClass:$rs2)),
|
||
|
|
(!cast<Instruction>("PseudoVMERGE_VIM_"#vti.LMul.MX)
|
||
|
|
vti.RegClass:$rs2, simm5:$rs1, VMV0:$vm, vti.AVL, vti.SEW)>;
|
||
|
|
}
|
||
|
|
|
||
|
|
// 16.1. Vector Mask-Register Logical Instructions
|
||
|
|
foreach mti = AllMasks in {
|
||
|
|
def : Pat<(mti.Mask (and VR:$rs1, VR:$rs2)),
|
||
|
|
(!cast<Instruction>("PseudoVMAND_MM_"#mti.LMul.MX)
|
||
|
|
VR:$rs1, VR:$rs2, mti.AVL, mti.SEW)>;
|
||
|
|
def : Pat<(mti.Mask (or VR:$rs1, VR:$rs2)),
|
||
|
|
(!cast<Instruction>("PseudoVMOR_MM_"#mti.LMul.MX)
|
||
|
|
VR:$rs1, VR:$rs2, mti.AVL, mti.SEW)>;
|
||
|
|
def : Pat<(mti.Mask (xor VR:$rs1, VR:$rs2)),
|
||
|
|
(!cast<Instruction>("PseudoVMXOR_MM_"#mti.LMul.MX)
|
||
|
|
VR:$rs1, VR:$rs2, mti.AVL, mti.SEW)>;
|
||
|
|
|
||
|
|
def : Pat<(mti.Mask (vnot (and VR:$rs1, VR:$rs2))),
|
||
|
|
(!cast<Instruction>("PseudoVMNAND_MM_"#mti.LMul.MX)
|
||
|
|
VR:$rs1, VR:$rs2, mti.AVL, mti.SEW)>;
|
||
|
|
def : Pat<(mti.Mask (vnot (or VR:$rs1, VR:$rs2))),
|
||
|
|
(!cast<Instruction>("PseudoVMNOR_MM_"#mti.LMul.MX)
|
||
|
|
VR:$rs1, VR:$rs2, mti.AVL, mti.SEW)>;
|
||
|
|
def : Pat<(mti.Mask (vnot (xor VR:$rs1, VR:$rs2))),
|
||
|
|
(!cast<Instruction>("PseudoVMXNOR_MM_"#mti.LMul.MX)
|
||
|
|
VR:$rs1, VR:$rs2, mti.AVL, mti.SEW)>;
|
||
|
|
|
||
|
|
def : Pat<(mti.Mask (and VR:$rs1, (vnot VR:$rs2))),
|
||
|
|
(!cast<Instruction>("PseudoVMANDNOT_MM_"#mti.LMul.MX)
|
||
|
|
VR:$rs1, VR:$rs2, mti.AVL, mti.SEW)>;
|
||
|
|
def : Pat<(mti.Mask (or VR:$rs1, (vnot VR:$rs2))),
|
||
|
|
(!cast<Instruction>("PseudoVMORNOT_MM_"#mti.LMul.MX)
|
||
|
|
VR:$rs1, VR:$rs2, mti.AVL, mti.SEW)>;
|
||
|
|
}
|
||
|
|
|
||
|
|
} // Predicates = [HasStdExtV]
|
||
|
|
|
||
|
|
let Predicates = [HasStdExtV, HasStdExtF] in {
|
||
|
|
|
||
|
|
// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions
|
||
|
|
defm "" : VPatBinaryFPSDNode_VV_VF<fadd, "PseudoVFADD">;
|
||
|
|
defm "" : VPatBinaryFPSDNode_VV_VF<fsub, "PseudoVFSUB">;
|
||
|
|
defm "" : VPatBinaryFPSDNode_R_VF<fsub, "PseudoVFRSUB">;
|
||
|
|
|
||
|
|
// 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
|
||
|
|
defm "" : VPatBinaryFPSDNode_VV_VF<fmul, "PseudoVFMUL">;
|
||
|
|
defm "" : VPatBinaryFPSDNode_VV_VF<fdiv, "PseudoVFDIV">;
|
||
|
|
defm "" : VPatBinaryFPSDNode_R_VF<fdiv, "PseudoVFRDIV">;
|
||
|
|
|
||
|
|
// 14.11. Vector Floating-Point Compare Instructions
|
||
|
|
defm "" : VPatFPSetCCSDNode_VV_VF_FV<SETEQ, "PseudoVMFEQ", "PseudoVMFEQ">;
|
||
|
|
defm "" : VPatFPSetCCSDNode_VV_VF_FV<SETOEQ, "PseudoVMFEQ", "PseudoVMFEQ">;
|
||
|
|
|
||
|
|
defm "" : VPatFPSetCCSDNode_VV_VF_FV<SETNE, "PseudoVMFNE", "PseudoVMFNE">;
|
||
|
|
defm "" : VPatFPSetCCSDNode_VV_VF_FV<SETUNE, "PseudoVMFNE", "PseudoVMFNE">;
|
||
|
|
|
||
|
|
defm "" : VPatFPSetCCSDNode_VV_VF_FV<SETLT, "PseudoVMFLT", "PseudoVMFGT">;
|
||
|
|
defm "" : VPatFPSetCCSDNode_VV_VF_FV<SETOLT, "PseudoVMFLT", "PseudoVMFGT">;
|
||
|
|
|
||
|
|
defm "" : VPatFPSetCCSDNode_VV_VF_FV<SETLE, "PseudoVMFLE", "PseudoVMFGE">;
|
||
|
|
defm "" : VPatFPSetCCSDNode_VV_VF_FV<SETOLE, "PseudoVMFLE", "PseudoVMFGE">;
|
||
|
|
|
||
|
|
// Floating-point vselects:
|
||
|
|
// 12.16. Vector Integer Merge Instructions
|
||
|
|
// 14.13. Vector Floating-Point Merge Instruction
|
||
|
|
foreach fvti = AllFloatVectors in {
|
||
|
|
def : Pat<(fvti.Vector (vselect (fvti.Mask VMV0:$vm), fvti.RegClass:$rs1,
|
||
|
|
fvti.RegClass:$rs2)),
|
||
|
|
(!cast<Instruction>("PseudoVMERGE_VVM_"#fvti.LMul.MX)
|
||
|
|
fvti.RegClass:$rs2, fvti.RegClass:$rs1, VMV0:$vm,
|
||
|
|
fvti.AVL, fvti.SEW)>;
|
||
|
|
|
||
|
|
def : Pat<(fvti.Vector (vselect (fvti.Mask VMV0:$vm),
|
||
|
|
(splat_vector fvti.ScalarRegClass:$rs1),
|
||
|
|
fvti.RegClass:$rs2)),
|
||
|
|
(!cast<Instruction>("PseudoVFMERGE_V"#fvti.ScalarSuffix#"M_"#fvti.LMul.MX)
|
||
|
|
fvti.RegClass:$rs2,
|
||
|
|
(fvti.Scalar fvti.ScalarRegClass:$rs1),
|
||
|
|
VMV0:$vm, fvti.AVL, fvti.SEW)>;
|
||
|
|
|
||
|
|
def : Pat<(fvti.Vector (vselect (fvti.Mask VMV0:$vm),
|
||
|
|
(splat_vector (fvti.Scalar fpimm0)),
|
||
|
|
fvti.RegClass:$rs2)),
|
||
|
|
(!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX)
|
||
|
|
fvti.RegClass:$rs2, 0, VMV0:$vm, fvti.AVL, fvti.SEW)>;
|
||
|
|
}
|
||
|
|
} // Predicates = [HasStdExtV, HasStdExtF]
|
||
|
|
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
// Vector Splats
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
|
||
|
|
let Predicates = [HasStdExtV] in {
|
||
|
|
foreach vti = AllIntegerVectors in {
|
||
|
|
def : Pat<(vti.Vector (splat_vector GPR:$rs1)),
|
||
|
|
(!cast<Instruction>("PseudoVMV_V_X_" # vti.LMul.MX)
|
||
|
|
GPR:$rs1, vti.AVL, vti.SEW)>;
|
||
|
|
def : Pat<(vti.Vector (splat_vector simm5:$rs1)),
|
||
|
|
(!cast<Instruction>("PseudoVMV_V_I_" # vti.LMul.MX)
|
||
|
|
simm5:$rs1, vti.AVL, vti.SEW)>;
|
||
|
|
}
|
||
|
|
|
||
|
|
foreach mti = AllMasks in {
|
||
|
|
def : Pat<(mti.Mask immAllOnesV),
|
||
|
|
(!cast<Instruction>("PseudoVMSET_M_"#mti.BX) mti.AVL, mti.SEW)>;
|
||
|
|
def : Pat<(mti.Mask immAllZerosV),
|
||
|
|
(!cast<Instruction>("PseudoVMCLR_M_"#mti.BX) mti.AVL, mti.SEW)>;
|
||
|
|
}
|
||
|
|
} // Predicates = [HasStdExtV]
|
||
|
|
|
||
|
|
let Predicates = [HasStdExtV, IsRV32] in {
|
||
|
|
foreach vti = AllIntegerVectors in {
|
||
|
|
if !eq(vti.SEW, 64) then {
|
||
|
|
def : Pat<(vti.Vector (rv32_splat_i64 GPR:$rs1)),
|
||
|
|
(!cast<Instruction>("PseudoVMV_V_X_" # vti.LMul.MX)
|
||
|
|
GPR:$rs1, vti.AVL, vti.SEW)>;
|
||
|
|
def : Pat<(vti.Vector (rv32_splat_i64 simm5:$rs1)),
|
||
|
|
(!cast<Instruction>("PseudoVMV_V_I_" # vti.LMul.MX)
|
||
|
|
simm5:$rs1, vti.AVL, vti.SEW)>;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
} // Predicates = [HasStdExtV, IsRV32]
|
||
|
|
|
||
|
|
let Predicates = [HasStdExtV, HasStdExtF] in {
|
||
|
|
foreach fvti = AllFloatVectors in {
|
||
|
|
def : Pat<(fvti.Vector (splat_vector fvti.ScalarRegClass:$rs1)),
|
||
|
|
(!cast<Instruction>("PseudoVFMV_V_"#fvti.ScalarSuffix#"_"#fvti.LMul.MX)
|
||
|
|
(fvti.Scalar fvti.ScalarRegClass:$rs1),
|
||
|
|
fvti.AVL, fvti.SEW)>;
|
||
|
|
|
||
|
|
def : Pat<(fvti.Vector (splat_vector (fvti.Scalar fpimm0))),
|
||
|
|
(!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX)
|
||
|
|
0, fvti.AVL, fvti.SEW)>;
|
||
|
|
}
|
||
|
|
} // Predicates = [HasStdExtV, HasStdExtF]
|
||
|
|
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
// Vector Element Inserts/Extracts
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
|
||
|
|
// The built-in TableGen 'extractelt' and 'insertelt' nodes must return the
|
||
|
|
// same type as the vector element type. On RISC-V, XLenVT is the only legal
|
||
|
|
// integer type, so for integer inserts/extracts we use a custom node which
|
||
|
|
// returns XLenVT.
|
||
|
|
def riscv_insert_vector_elt
|
||
|
|
: SDNode<"ISD::INSERT_VECTOR_ELT",
|
||
|
|
SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, XLenVT>,
|
||
|
|
SDTCisPtrTy<3>]>, []>;
|
||
|
|
def riscv_extract_vector_elt
|
||
|
|
: SDNode<"ISD::EXTRACT_VECTOR_ELT",
|
||
|
|
SDTypeProfile<1, 2, [SDTCisVT<0, XLenVT>, SDTCisPtrTy<2>]>, []>;
|
||
|
|
|
||
|
|
multiclass VPatInsertExtractElt_XI_Idx<bit IsFloat> {
|
||
|
|
defvar vtilist = !if(IsFloat, AllFloatVectors, AllIntegerVectors);
|
||
|
|
defvar insertelt_node = !if(IsFloat, insertelt, riscv_insert_vector_elt);
|
||
|
|
defvar extractelt_node = !if(IsFloat, extractelt, riscv_extract_vector_elt);
|
||
|
|
foreach vti = vtilist in {
|
||
|
|
defvar MX = vti.LMul.MX;
|
||
|
|
defvar vmv_xf_s_inst = !cast<Instruction>(!strconcat("PseudoV",
|
||
|
|
!if(IsFloat, "F", ""),
|
||
|
|
"MV_",
|
||
|
|
vti.ScalarSuffix,
|
||
|
|
"_S_", MX));
|
||
|
|
defvar vmv_s_xf_inst = !cast<Instruction>(!strconcat("PseudoV",
|
||
|
|
!if(IsFloat, "F", ""),
|
||
|
|
"MV_S_",
|
||
|
|
vti.ScalarSuffix,
|
||
|
|
"_", MX));
|
||
|
|
// Only pattern-match insert/extract-element operations where the index is
|
||
|
|
// 0. Any other index will have been custom-lowered to slide the vector
|
||
|
|
// correctly into place (and, in the case of insert, slide it back again
|
||
|
|
// afterwards).
|
||
|
|
def : Pat<(vti.Scalar (extractelt_node (vti.Vector vti.RegClass:$rs2), 0)),
|
||
|
|
(vmv_xf_s_inst vti.RegClass:$rs2, vti.SEW)>;
|
||
|
|
|
||
|
|
def : Pat<(vti.Vector (insertelt_node (vti.Vector vti.RegClass:$merge),
|
||
|
|
vti.ScalarRegClass:$rs1, 0)),
|
||
|
|
(vmv_s_xf_inst vti.RegClass:$merge,
|
||
|
|
(vti.Scalar vti.ScalarRegClass:$rs1),
|
||
|
|
vti.AVL, vti.SEW)>;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
let Predicates = [HasStdExtV] in
|
||
|
|
defm "" : VPatInsertExtractElt_XI_Idx</*IsFloat*/0>;
|
||
|
|
let Predicates = [HasStdExtV, HasStdExtF] in
|
||
|
|
defm "" : VPatInsertExtractElt_XI_Idx</*IsFloat*/1>;
|
||
|
|
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
// Miscellaneous RISCVISD SDNodes
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
|
||
|
|
def riscv_vid
|
||
|
|
: SDNode<"RISCVISD::VID", SDTypeProfile<1, 0, [SDTCisVec<0>]>, []>;
|
||
|
|
|
||
|
|
def SDTRVVSlide : SDTypeProfile<1, 3, [
|
||
|
|
SDTCisVec<0>, SDTCisSameAs<1, 0>, SDTCisSameAs<2, 0>, SDTCisVT<3, XLenVT>
|
||
|
|
]>;
|
||
|
|
|
||
|
|
def riscv_slideup : SDNode<"RISCVISD::VSLIDEUP", SDTRVVSlide, []>;
|
||
|
|
def riscv_slidedown : SDNode<"RISCVISD::VSLIDEDOWN", SDTRVVSlide, []>;
|
||
|
|
|
||
|
|
let Predicates = [HasStdExtV] in {
|
||
|
|
|
||
|
|
foreach vti = AllIntegerVectors in
|
||
|
|
def : Pat<(vti.Vector riscv_vid),
|
||
|
|
(!cast<Instruction>("PseudoVID_V_"#vti.LMul.MX) vti.AVL, vti.SEW)>;
|
||
|
|
|
||
|
|
foreach vti = !listconcat(AllIntegerVectors, AllFloatVectors) in {
|
||
|
|
def : Pat<(vti.Vector (riscv_slideup (vti.Vector vti.RegClass:$rs3),
|
||
|
|
(vti.Vector vti.RegClass:$rs1),
|
||
|
|
uimm5:$rs2)),
|
||
|
|
(!cast<Instruction>("PseudoVSLIDEUP_VI_"#vti.LMul.MX)
|
||
|
|
vti.RegClass:$rs3, vti.RegClass:$rs1, uimm5:$rs2,
|
||
|
|
vti.AVL, vti.SEW)>;
|
||
|
|
|
||
|
|
def : Pat<(vti.Vector (riscv_slideup (vti.Vector vti.RegClass:$rs3),
|
||
|
|
(vti.Vector vti.RegClass:$rs1),
|
||
|
|
GPR:$rs2)),
|
||
|
|
(!cast<Instruction>("PseudoVSLIDEUP_VX_"#vti.LMul.MX)
|
||
|
|
vti.RegClass:$rs3, vti.RegClass:$rs1, GPR:$rs2,
|
||
|
|
vti.AVL, vti.SEW)>;
|
||
|
|
|
||
|
|
def : Pat<(vti.Vector (riscv_slidedown (vti.Vector vti.RegClass:$rs3),
|
||
|
|
(vti.Vector vti.RegClass:$rs1),
|
||
|
|
uimm5:$rs2)),
|
||
|
|
(!cast<Instruction>("PseudoVSLIDEDOWN_VI_"#vti.LMul.MX)
|
||
|
|
vti.RegClass:$rs3, vti.RegClass:$rs1, uimm5:$rs2,
|
||
|
|
vti.AVL, vti.SEW)>;
|
||
|
|
|
||
|
|
def : Pat<(vti.Vector (riscv_slidedown (vti.Vector vti.RegClass:$rs3),
|
||
|
|
(vti.Vector vti.RegClass:$rs1),
|
||
|
|
GPR:$rs2)),
|
||
|
|
(!cast<Instruction>("PseudoVSLIDEDOWN_VX_"#vti.LMul.MX)
|
||
|
|
vti.RegClass:$rs3, vti.RegClass:$rs1, GPR:$rs2,
|
||
|
|
vti.AVL, vti.SEW)>;
|
||
|
|
}
|
||
|
|
} // Predicates = [HasStdExtV]
|