395 lines
13 KiB
TableGen
395 lines
13 KiB
TableGen
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//===-- RISCVInstrFormats.td - RISCV Instruction Formats ---*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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//
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// These instruction format definitions are structured to match the
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// description in the RISC-V User-Level ISA specification as closely as
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// possible. For instance, the specification describes instructions with the
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// MSB (31st bit) on the left and the LSB (0th bit) on the right. This is
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// reflected in the order of parameters to each instruction class.
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//
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// One area of divergence is in the description of immediates. The
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// specification describes immediate encoding in terms of bit-slicing
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// operations on the logical value represented. The immediate argument to
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// these instruction formats instead represents the bit sequence that will be
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// inserted into the instruction. e.g. although JAL's immediate is logically
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// a 21-bit value (where the LSB is always zero), we describe it as an imm20
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// to match how it is encoded.
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//
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//===----------------------------------------------------------------------===//
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// Format specifies the encoding used by the instruction. This is used by
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// RISCVMCCodeEmitter to determine which form of fixup to use. These
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// definitions must be kept in-sync with RISCVBaseInfo.h.
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class InstFormat<bits<5> val> {
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bits<5> Value = val;
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}
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def InstFormatPseudo : InstFormat<0>;
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def InstFormatR : InstFormat<1>;
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def InstFormatR4 : InstFormat<2>;
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def InstFormatI : InstFormat<3>;
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def InstFormatS : InstFormat<4>;
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def InstFormatB : InstFormat<5>;
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def InstFormatU : InstFormat<6>;
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def InstFormatJ : InstFormat<7>;
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def InstFormatCR : InstFormat<8>;
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def InstFormatCI : InstFormat<9>;
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def InstFormatCSS : InstFormat<10>;
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def InstFormatCIW : InstFormat<11>;
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def InstFormatCL : InstFormat<12>;
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def InstFormatCS : InstFormat<13>;
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def InstFormatCA : InstFormat<14>;
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def InstFormatCB : InstFormat<15>;
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def InstFormatCJ : InstFormat<16>;
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def InstFormatOther : InstFormat<17>;
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class RISCVVConstraint<bits<3> val> {
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bits<3> Value = val;
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}
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def NoConstraint : RISCVVConstraint<0b000>;
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def VS2Constraint : RISCVVConstraint<0b001>;
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def VS1Constraint : RISCVVConstraint<0b010>;
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def VMConstraint : RISCVVConstraint<0b100>;
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// Illegal instructions:
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//
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// * The destination vector register group for a masked vector instruction
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// cannot overlap the source mask register (v0), unless the destination vector
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// register is being written with a mask value (e.g., comparisons) or the
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// scalar result of a reduction.
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//
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// * Widening: The destination EEW is greater than the source EEW, the source
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// EMUL is at least 1. The destination vector register group cannot overlap
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// with the source vector register groups besides the highest-numbered part of
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// the destination register group.
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//
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// * Narrowing: The destination EEW is smaller than the source EEW. The
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// destination vector register group cannot overlap with the source vector
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// register groups besides the lowest-numbered part of the source register
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// group.
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//
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// * vmsbf.m/vmsif.m/vmsof.m: The destination register cannot overlap the
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// source register and, if masked, cannot overlap the mask register ('v0').
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//
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// * viota: The destination register cannot overlap the source register and,
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// if masked, cannot overlap the mask register ('v0').
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//
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// * v[f]slide[1]up: The destination vector register group for vslideup cannot
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// overlap the source vector register group.
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//
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// * vrgather: The destination vector register group cannot overlap with the
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// source vector register groups.
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//
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// * vcompress: The destination vector register group cannot overlap the
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// source vector register group or the source mask register
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def WidenV : RISCVVConstraint<!or(VS2Constraint.Value,
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VS1Constraint.Value,
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VMConstraint.Value)>;
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def WidenW : RISCVVConstraint<!or(VS1Constraint.Value,
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VMConstraint.Value)>;
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def WidenCvt : RISCVVConstraint<!or(VS2Constraint.Value,
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VMConstraint.Value)>;
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def Iota : RISCVVConstraint<!or(VS2Constraint.Value,
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VMConstraint.Value)>;
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def SlideUp : RISCVVConstraint<!or(VS2Constraint.Value,
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VMConstraint.Value)>;
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def Vrgather : RISCVVConstraint<!or(VS2Constraint.Value,
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VS1Constraint.Value,
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VMConstraint.Value)>;
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def Vcompress : RISCVVConstraint<!or(VS2Constraint.Value,
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VS1Constraint.Value)>;
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// The following opcode names match those given in Table 19.1 in the
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// RISC-V User-level ISA specification ("RISC-V base opcode map").
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class RISCVOpcode<bits<7> val> {
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bits<7> Value = val;
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}
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def OPC_LOAD : RISCVOpcode<0b0000011>;
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def OPC_LOAD_FP : RISCVOpcode<0b0000111>;
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def OPC_MISC_MEM : RISCVOpcode<0b0001111>;
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def OPC_OP_IMM : RISCVOpcode<0b0010011>;
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def OPC_AUIPC : RISCVOpcode<0b0010111>;
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def OPC_OP_IMM_32 : RISCVOpcode<0b0011011>;
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def OPC_STORE : RISCVOpcode<0b0100011>;
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def OPC_STORE_FP : RISCVOpcode<0b0100111>;
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def OPC_AMO : RISCVOpcode<0b0101111>;
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def OPC_OP : RISCVOpcode<0b0110011>;
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def OPC_LUI : RISCVOpcode<0b0110111>;
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def OPC_OP_32 : RISCVOpcode<0b0111011>;
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def OPC_MADD : RISCVOpcode<0b1000011>;
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def OPC_MSUB : RISCVOpcode<0b1000111>;
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def OPC_NMSUB : RISCVOpcode<0b1001011>;
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def OPC_NMADD : RISCVOpcode<0b1001111>;
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def OPC_OP_FP : RISCVOpcode<0b1010011>;
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def OPC_OP_V : RISCVOpcode<0b1010111>;
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def OPC_BRANCH : RISCVOpcode<0b1100011>;
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def OPC_JALR : RISCVOpcode<0b1100111>;
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def OPC_JAL : RISCVOpcode<0b1101111>;
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def OPC_SYSTEM : RISCVOpcode<0b1110011>;
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class RVInst<dag outs, dag ins, string opcodestr, string argstr,
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list<dag> pattern, InstFormat format>
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: Instruction {
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field bits<32> Inst;
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// SoftFail is a field the disassembler can use to provide a way for
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// instructions to not match without killing the whole decode process. It is
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// mainly used for ARM, but Tablegen expects this field to exist or it fails
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// to build the decode table.
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field bits<32> SoftFail = 0;
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let Size = 4;
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bits<7> Opcode = 0;
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let Inst{6-0} = Opcode;
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let Namespace = "RISCV";
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dag OutOperandList = outs;
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dag InOperandList = ins;
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let AsmString = opcodestr # "\t" # argstr;
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let Pattern = pattern;
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let TSFlags{4-0} = format.Value;
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// Defaults
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RISCVVConstraint RVVConstraint = NoConstraint;
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let TSFlags{7-5} = RVVConstraint.Value;
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bits<3> VLMul = 0;
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let TSFlags{10-8} = VLMul;
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bit HasDummyMask = 0;
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let TSFlags{11} = HasDummyMask;
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bit WritesElement0 = 0;
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let TSFlags{12} = WritesElement0;
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bit HasMergeOp = 0;
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let TSFlags{13} = HasMergeOp;
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bit HasSEWOp = 0;
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let TSFlags{14} = HasSEWOp;
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bit HasVLOp = 0;
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let TSFlags{15} = HasVLOp;
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}
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// Pseudo instructions
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class Pseudo<dag outs, dag ins, list<dag> pattern, string opcodestr = "", string argstr = "">
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: RVInst<outs, ins, opcodestr, argstr, pattern, InstFormatPseudo>,
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Sched<[]> {
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let isPseudo = 1;
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let isCodeGenOnly = 1;
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}
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// Pseudo load instructions.
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class PseudoLoad<string opcodestr, RegisterClass rdty = GPR>
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: Pseudo<(outs rdty:$rd), (ins bare_symbol:$addr), [], opcodestr, "$rd, $addr"> {
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let hasSideEffects = 0;
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let mayLoad = 1;
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let mayStore = 0;
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let isCodeGenOnly = 0;
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let isAsmParserOnly = 1;
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}
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class PseudoFloatLoad<string opcodestr, RegisterClass rdty = GPR>
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: Pseudo<(outs rdty:$rd, GPR:$tmp), (ins bare_symbol:$addr), [], opcodestr, "$rd, $addr, $tmp"> {
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let hasSideEffects = 0;
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let mayLoad = 1;
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let mayStore = 0;
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let isCodeGenOnly = 0;
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let isAsmParserOnly = 1;
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}
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// Pseudo store instructions.
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class PseudoStore<string opcodestr, RegisterClass rsty = GPR>
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: Pseudo<(outs rsty:$rs, GPR:$tmp), (ins bare_symbol:$addr), [], opcodestr, "$rs, $addr, $tmp"> {
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let hasSideEffects = 0;
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let mayLoad = 0;
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let mayStore = 1;
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let isCodeGenOnly = 0;
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let isAsmParserOnly = 1;
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}
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// Instruction formats are listed in the order they appear in the RISC-V
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// instruction set manual (R, I, S, B, U, J) with sub-formats (e.g. RVInstR4,
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// RVInstRAtomic) sorted alphabetically.
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class RVInstR<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode, dag outs,
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dag ins, string opcodestr, string argstr>
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: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
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bits<5> rs2;
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bits<5> rs1;
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bits<5> rd;
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let Inst{31-25} = funct7;
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let Inst{24-20} = rs2;
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let Inst{19-15} = rs1;
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let Inst{14-12} = funct3;
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let Inst{11-7} = rd;
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let Opcode = opcode.Value;
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}
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class RVInstR4<bits<2> funct2, RISCVOpcode opcode, dag outs, dag ins,
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string opcodestr, string argstr>
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: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR4> {
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bits<5> rs3;
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bits<5> rs2;
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bits<5> rs1;
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bits<3> funct3;
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bits<5> rd;
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let Inst{31-27} = rs3;
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let Inst{26-25} = funct2;
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let Inst{24-20} = rs2;
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let Inst{19-15} = rs1;
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let Inst{14-12} = funct3;
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let Inst{11-7} = rd;
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let Opcode = opcode.Value;
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}
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class RVInstRAtomic<bits<5> funct5, bit aq, bit rl, bits<3> funct3,
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RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
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string argstr>
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: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
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bits<5> rs2;
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bits<5> rs1;
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bits<5> rd;
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let Inst{31-27} = funct5;
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let Inst{26} = aq;
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let Inst{25} = rl;
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let Inst{24-20} = rs2;
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let Inst{19-15} = rs1;
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let Inst{14-12} = funct3;
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let Inst{11-7} = rd;
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let Opcode = opcode.Value;
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}
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class RVInstRFrm<bits<7> funct7, RISCVOpcode opcode, dag outs, dag ins,
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string opcodestr, string argstr>
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: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
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bits<5> rs2;
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bits<5> rs1;
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bits<3> funct3;
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bits<5> rd;
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let Inst{31-25} = funct7;
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let Inst{24-20} = rs2;
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let Inst{19-15} = rs1;
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let Inst{14-12} = funct3;
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let Inst{11-7} = rd;
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let Opcode = opcode.Value;
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}
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class RVInstI<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
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string opcodestr, string argstr>
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: RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
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bits<12> imm12;
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bits<5> rs1;
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bits<5> rd;
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let Inst{31-20} = imm12;
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let Inst{19-15} = rs1;
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let Inst{14-12} = funct3;
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let Inst{11-7} = rd;
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let Opcode = opcode.Value;
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}
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class RVInstIShift<bit arithshift, bits<3> funct3, RISCVOpcode opcode,
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dag outs, dag ins, string opcodestr, string argstr>
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: RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
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bits<6> shamt;
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bits<5> rs1;
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bits<5> rd;
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let Inst{31} = 0;
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let Inst{30} = arithshift;
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let Inst{29-26} = 0;
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let Inst{25-20} = shamt;
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let Inst{19-15} = rs1;
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let Inst{14-12} = funct3;
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let Inst{11-7} = rd;
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let Opcode = opcode.Value;
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}
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class RVInstIShiftW<bit arithshift, bits<3> funct3, RISCVOpcode opcode,
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dag outs, dag ins, string opcodestr, string argstr>
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: RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
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bits<5> shamt;
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bits<5> rs1;
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bits<5> rd;
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let Inst{31} = 0;
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let Inst{30} = arithshift;
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let Inst{29-25} = 0;
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let Inst{24-20} = shamt;
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let Inst{19-15} = rs1;
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let Inst{14-12} = funct3;
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let Inst{11-7} = rd;
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let Opcode = opcode.Value;
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}
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class RVInstS<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
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string opcodestr, string argstr>
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: RVInst<outs, ins, opcodestr, argstr, [], InstFormatS> {
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bits<12> imm12;
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bits<5> rs2;
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bits<5> rs1;
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let Inst{31-25} = imm12{11-5};
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let Inst{24-20} = rs2;
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let Inst{19-15} = rs1;
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let Inst{14-12} = funct3;
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let Inst{11-7} = imm12{4-0};
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let Opcode = opcode.Value;
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}
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class RVInstB<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
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string opcodestr, string argstr>
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: RVInst<outs, ins, opcodestr, argstr, [], InstFormatB> {
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bits<12> imm12;
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bits<5> rs2;
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bits<5> rs1;
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let Inst{31} = imm12{11};
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let Inst{30-25} = imm12{9-4};
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let Inst{24-20} = rs2;
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let Inst{19-15} = rs1;
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let Inst{14-12} = funct3;
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let Inst{11-8} = imm12{3-0};
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let Inst{7} = imm12{10};
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let Opcode = opcode.Value;
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}
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class RVInstU<RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
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string argstr>
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: RVInst<outs, ins, opcodestr, argstr, [], InstFormatU> {
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bits<20> imm20;
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bits<5> rd;
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let Inst{31-12} = imm20;
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let Inst{11-7} = rd;
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let Opcode = opcode.Value;
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}
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class RVInstJ<RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
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string argstr>
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: RVInst<outs, ins, opcodestr, argstr, [], InstFormatJ> {
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bits<20> imm20;
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bits<5> rd;
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let Inst{31} = imm20{19};
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let Inst{30-21} = imm20{9-0};
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let Inst{20} = imm20{10};
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let Inst{19-12} = imm20{18-11};
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let Inst{11-7} = rd;
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let Opcode = opcode.Value;
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}
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