410 lines
15 KiB
C++
410 lines
15 KiB
C++
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//===-- RISCVMCCodeEmitter.cpp - Convert RISCV code to machine code -------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the RISCVMCCodeEmitter class.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/RISCVBaseInfo.h"
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#include "MCTargetDesc/RISCVFixupKinds.h"
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#include "MCTargetDesc/RISCVMCExpr.h"
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstBuilder.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/EndianStream.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "mccodeemitter"
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STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
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STATISTIC(MCNumFixups, "Number of MC fixups created");
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namespace {
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class RISCVMCCodeEmitter : public MCCodeEmitter {
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RISCVMCCodeEmitter(const RISCVMCCodeEmitter &) = delete;
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void operator=(const RISCVMCCodeEmitter &) = delete;
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MCContext &Ctx;
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MCInstrInfo const &MCII;
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public:
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RISCVMCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII)
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: Ctx(ctx), MCII(MCII) {}
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~RISCVMCCodeEmitter() override {}
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void encodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const override;
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void expandFunctionCall(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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void expandAddTPRel(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// TableGen'erated function for getting the binary encoding for an
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/// instruction.
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uint64_t getBinaryCodeForInstr(const MCInst &MI,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// Return binary encoding of operand. If the machine operand requires
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/// relocation, record the relocation and return zero.
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unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getImmOpValue(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getVMaskReg(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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private:
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FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) const;
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void
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verifyInstructionPredicates(const MCInst &MI,
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const FeatureBitset &AvailableFeatures) const;
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};
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} // end anonymous namespace
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MCCodeEmitter *llvm::createRISCVMCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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MCContext &Ctx) {
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return new RISCVMCCodeEmitter(Ctx, MCII);
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}
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// Expand PseudoCALL(Reg), PseudoTAIL and PseudoJump to AUIPC and JALR with
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// relocation types. We expand those pseudo-instructions while encoding them,
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// meaning AUIPC and JALR won't go through RISCV MC to MC compressed
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// instruction transformation. This is acceptable because AUIPC has no 16-bit
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// form and C_JALR has no immediate operand field. We let linker relaxation
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// deal with it. When linker relaxation is enabled, AUIPC and JALR have a
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// chance to relax to JAL.
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// If the C extension is enabled, JAL has a chance relax to C_JAL.
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void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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MCInst TmpInst;
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MCOperand Func;
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MCRegister Ra;
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if (MI.getOpcode() == RISCV::PseudoTAIL) {
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Func = MI.getOperand(0);
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Ra = RISCV::X6;
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} else if (MI.getOpcode() == RISCV::PseudoCALLReg) {
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Func = MI.getOperand(1);
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Ra = MI.getOperand(0).getReg();
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} else if (MI.getOpcode() == RISCV::PseudoCALL) {
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Func = MI.getOperand(0);
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Ra = RISCV::X1;
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} else if (MI.getOpcode() == RISCV::PseudoJump) {
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Func = MI.getOperand(1);
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Ra = MI.getOperand(0).getReg();
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}
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uint32_t Binary;
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assert(Func.isExpr() && "Expected expression");
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const MCExpr *CallExpr = Func.getExpr();
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// Emit AUIPC Ra, Func with R_RISCV_CALL relocation type.
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TmpInst = MCInstBuilder(RISCV::AUIPC)
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.addReg(Ra)
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.addOperand(MCOperand::createExpr(CallExpr));
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Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
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support::endian::write(OS, Binary, support::little);
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if (MI.getOpcode() == RISCV::PseudoTAIL ||
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MI.getOpcode() == RISCV::PseudoJump)
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// Emit JALR X0, Ra, 0
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TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0);
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else
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// Emit JALR Ra, Ra, 0
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TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0);
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Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
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support::endian::write(OS, Binary, support::little);
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}
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// Expand PseudoAddTPRel to a simple ADD with the correct relocation.
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void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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MCOperand DestReg = MI.getOperand(0);
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MCOperand SrcReg = MI.getOperand(1);
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MCOperand TPReg = MI.getOperand(2);
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assert(TPReg.isReg() && TPReg.getReg() == RISCV::X4 &&
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"Expected thread pointer as second input to TP-relative add");
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MCOperand SrcSymbol = MI.getOperand(3);
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assert(SrcSymbol.isExpr() &&
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"Expected expression as third input to TP-relative add");
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const RISCVMCExpr *Expr = dyn_cast<RISCVMCExpr>(SrcSymbol.getExpr());
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assert(Expr && Expr->getKind() == RISCVMCExpr::VK_RISCV_TPREL_ADD &&
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"Expected tprel_add relocation on TP-relative symbol");
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// Emit the correct tprel_add relocation for the symbol.
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Fixups.push_back(MCFixup::create(
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0, Expr, MCFixupKind(RISCV::fixup_riscv_tprel_add), MI.getLoc()));
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// Emit fixup_riscv_relax for tprel_add where the relax feature is enabled.
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if (STI.getFeatureBits()[RISCV::FeatureRelax]) {
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const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx);
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Fixups.push_back(MCFixup::create(
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0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax), MI.getLoc()));
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}
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// Emit a normal ADD instruction with the given operands.
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MCInst TmpInst = MCInstBuilder(RISCV::ADD)
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.addOperand(DestReg)
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.addOperand(SrcReg)
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.addOperand(TPReg);
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uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
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support::endian::write(OS, Binary, support::little);
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}
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void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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verifyInstructionPredicates(MI,
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computeAvailableFeatures(STI.getFeatureBits()));
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const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
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// Get byte count of instruction.
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unsigned Size = Desc.getSize();
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// RISCVInstrInfo::getInstSizeInBytes hard-codes the number of expanded
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// instructions for each pseudo, and must be updated when adding new pseudos
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// or changing existing ones.
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if (MI.getOpcode() == RISCV::PseudoCALLReg ||
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MI.getOpcode() == RISCV::PseudoCALL ||
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MI.getOpcode() == RISCV::PseudoTAIL ||
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MI.getOpcode() == RISCV::PseudoJump) {
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expandFunctionCall(MI, OS, Fixups, STI);
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MCNumEmitted += 2;
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return;
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}
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if (MI.getOpcode() == RISCV::PseudoAddTPRel) {
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expandAddTPRel(MI, OS, Fixups, STI);
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MCNumEmitted += 1;
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return;
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}
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switch (Size) {
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default:
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llvm_unreachable("Unhandled encodeInstruction length!");
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case 2: {
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uint16_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
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support::endian::write<uint16_t>(OS, Bits, support::little);
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break;
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}
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case 4: {
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uint32_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
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support::endian::write(OS, Bits, support::little);
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break;
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}
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}
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++MCNumEmitted; // Keep track of the # of mi's emitted.
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}
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unsigned
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RISCVMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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if (MO.isReg())
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return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
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if (MO.isImm())
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return static_cast<unsigned>(MO.getImm());
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llvm_unreachable("Unhandled expression!");
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return 0;
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}
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unsigned
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RISCVMCCodeEmitter::getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isImm()) {
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unsigned Res = MO.getImm();
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assert((Res & 1) == 0 && "LSB is non-zero");
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return Res >> 1;
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}
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return getImmOpValue(MI, OpNo, Fixups, STI);
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}
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unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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bool EnableRelax = STI.getFeatureBits()[RISCV::FeatureRelax];
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const MCOperand &MO = MI.getOperand(OpNo);
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MCInstrDesc const &Desc = MCII.get(MI.getOpcode());
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unsigned MIFrm = Desc.TSFlags & RISCVII::InstFormatMask;
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// If the destination is an immediate, there is nothing to do.
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if (MO.isImm())
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return MO.getImm();
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assert(MO.isExpr() &&
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"getImmOpValue expects only expressions or immediates");
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const MCExpr *Expr = MO.getExpr();
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MCExpr::ExprKind Kind = Expr->getKind();
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RISCV::Fixups FixupKind = RISCV::fixup_riscv_invalid;
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bool RelaxCandidate = false;
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if (Kind == MCExpr::Target) {
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const RISCVMCExpr *RVExpr = cast<RISCVMCExpr>(Expr);
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switch (RVExpr->getKind()) {
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case RISCVMCExpr::VK_RISCV_None:
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case RISCVMCExpr::VK_RISCV_Invalid:
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case RISCVMCExpr::VK_RISCV_32_PCREL:
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llvm_unreachable("Unhandled fixup kind!");
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case RISCVMCExpr::VK_RISCV_TPREL_ADD:
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// tprel_add is only used to indicate that a relocation should be emitted
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// for an add instruction used in TP-relative addressing. It should not be
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// expanded as if representing an actual instruction operand and so to
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// encounter it here is an error.
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llvm_unreachable(
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"VK_RISCV_TPREL_ADD should not represent an instruction operand");
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case RISCVMCExpr::VK_RISCV_LO:
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if (MIFrm == RISCVII::InstFormatI)
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FixupKind = RISCV::fixup_riscv_lo12_i;
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else if (MIFrm == RISCVII::InstFormatS)
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FixupKind = RISCV::fixup_riscv_lo12_s;
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else
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llvm_unreachable("VK_RISCV_LO used with unexpected instruction format");
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RelaxCandidate = true;
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break;
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case RISCVMCExpr::VK_RISCV_HI:
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FixupKind = RISCV::fixup_riscv_hi20;
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RelaxCandidate = true;
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break;
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case RISCVMCExpr::VK_RISCV_PCREL_LO:
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if (MIFrm == RISCVII::InstFormatI)
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FixupKind = RISCV::fixup_riscv_pcrel_lo12_i;
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else if (MIFrm == RISCVII::InstFormatS)
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FixupKind = RISCV::fixup_riscv_pcrel_lo12_s;
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else
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llvm_unreachable(
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"VK_RISCV_PCREL_LO used with unexpected instruction format");
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RelaxCandidate = true;
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break;
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case RISCVMCExpr::VK_RISCV_PCREL_HI:
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FixupKind = RISCV::fixup_riscv_pcrel_hi20;
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RelaxCandidate = true;
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break;
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case RISCVMCExpr::VK_RISCV_GOT_HI:
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FixupKind = RISCV::fixup_riscv_got_hi20;
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break;
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|
|
case RISCVMCExpr::VK_RISCV_TPREL_LO:
|
||
|
|
if (MIFrm == RISCVII::InstFormatI)
|
||
|
|
FixupKind = RISCV::fixup_riscv_tprel_lo12_i;
|
||
|
|
else if (MIFrm == RISCVII::InstFormatS)
|
||
|
|
FixupKind = RISCV::fixup_riscv_tprel_lo12_s;
|
||
|
|
else
|
||
|
|
llvm_unreachable(
|
||
|
|
"VK_RISCV_TPREL_LO used with unexpected instruction format");
|
||
|
|
RelaxCandidate = true;
|
||
|
|
break;
|
||
|
|
case RISCVMCExpr::VK_RISCV_TPREL_HI:
|
||
|
|
FixupKind = RISCV::fixup_riscv_tprel_hi20;
|
||
|
|
RelaxCandidate = true;
|
||
|
|
break;
|
||
|
|
case RISCVMCExpr::VK_RISCV_TLS_GOT_HI:
|
||
|
|
FixupKind = RISCV::fixup_riscv_tls_got_hi20;
|
||
|
|
break;
|
||
|
|
case RISCVMCExpr::VK_RISCV_TLS_GD_HI:
|
||
|
|
FixupKind = RISCV::fixup_riscv_tls_gd_hi20;
|
||
|
|
break;
|
||
|
|
case RISCVMCExpr::VK_RISCV_CALL:
|
||
|
|
FixupKind = RISCV::fixup_riscv_call;
|
||
|
|
RelaxCandidate = true;
|
||
|
|
break;
|
||
|
|
case RISCVMCExpr::VK_RISCV_CALL_PLT:
|
||
|
|
FixupKind = RISCV::fixup_riscv_call_plt;
|
||
|
|
RelaxCandidate = true;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
} else if (Kind == MCExpr::SymbolRef &&
|
||
|
|
cast<MCSymbolRefExpr>(Expr)->getKind() == MCSymbolRefExpr::VK_None) {
|
||
|
|
if (Desc.getOpcode() == RISCV::JAL) {
|
||
|
|
FixupKind = RISCV::fixup_riscv_jal;
|
||
|
|
} else if (MIFrm == RISCVII::InstFormatB) {
|
||
|
|
FixupKind = RISCV::fixup_riscv_branch;
|
||
|
|
} else if (MIFrm == RISCVII::InstFormatCJ) {
|
||
|
|
FixupKind = RISCV::fixup_riscv_rvc_jump;
|
||
|
|
} else if (MIFrm == RISCVII::InstFormatCB) {
|
||
|
|
FixupKind = RISCV::fixup_riscv_rvc_branch;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
assert(FixupKind != RISCV::fixup_riscv_invalid && "Unhandled expression!");
|
||
|
|
|
||
|
|
Fixups.push_back(
|
||
|
|
MCFixup::create(0, Expr, MCFixupKind(FixupKind), MI.getLoc()));
|
||
|
|
++MCNumFixups;
|
||
|
|
|
||
|
|
// Ensure an R_RISCV_RELAX relocation will be emitted if linker relaxation is
|
||
|
|
// enabled and the current fixup will result in a relocation that may be
|
||
|
|
// relaxed.
|
||
|
|
if (EnableRelax && RelaxCandidate) {
|
||
|
|
const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx);
|
||
|
|
Fixups.push_back(
|
||
|
|
MCFixup::create(0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax),
|
||
|
|
MI.getLoc()));
|
||
|
|
++MCNumFixups;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
unsigned RISCVMCCodeEmitter::getVMaskReg(const MCInst &MI, unsigned OpNo,
|
||
|
|
SmallVectorImpl<MCFixup> &Fixups,
|
||
|
|
const MCSubtargetInfo &STI) const {
|
||
|
|
MCOperand MO = MI.getOperand(OpNo);
|
||
|
|
assert(MO.isReg() && "Expected a register.");
|
||
|
|
|
||
|
|
switch (MO.getReg()) {
|
||
|
|
default:
|
||
|
|
llvm_unreachable("Invalid mask register.");
|
||
|
|
case RISCV::V0:
|
||
|
|
return 0;
|
||
|
|
case RISCV::NoRegister:
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#define ENABLE_INSTR_PREDICATE_VERIFIER
|
||
|
|
#include "RISCVGenMCCodeEmitter.inc"
|