477 lines
17 KiB
C++
477 lines
17 KiB
C++
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//===-- RISCVAsmBackend.cpp - RISCV Assembler Backend ---------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVAsmBackend.h"
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#include "RISCVMCExpr.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/MC/MCAsmLayout.h"
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDirectives.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/MC/MCValue.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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Optional<MCFixupKind> RISCVAsmBackend::getFixupKind(StringRef Name) const {
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if (STI.getTargetTriple().isOSBinFormatELF()) {
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unsigned Type;
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Type = llvm::StringSwitch<unsigned>(Name)
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#define ELF_RELOC(X, Y) .Case(#X, Y)
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#include "llvm/BinaryFormat/ELFRelocs/RISCV.def"
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#undef ELF_RELOC
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.Default(-1u);
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if (Type != -1u)
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return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
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}
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return None;
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}
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const MCFixupKindInfo &
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RISCVAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
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const static MCFixupKindInfo Infos[] = {
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// This table *must* be in the order that the fixup_* kinds are defined in
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// RISCVFixupKinds.h.
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//
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// name offset bits flags
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{"fixup_riscv_hi20", 12, 20, 0},
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{"fixup_riscv_lo12_i", 20, 12, 0},
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{"fixup_riscv_lo12_s", 0, 32, 0},
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{"fixup_riscv_pcrel_hi20", 12, 20,
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MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsTarget},
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{"fixup_riscv_pcrel_lo12_i", 20, 12,
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MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsTarget},
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{"fixup_riscv_pcrel_lo12_s", 0, 32,
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MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsTarget},
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{"fixup_riscv_got_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_riscv_tprel_hi20", 12, 20, 0},
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{"fixup_riscv_tprel_lo12_i", 20, 12, 0},
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{"fixup_riscv_tprel_lo12_s", 0, 32, 0},
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{"fixup_riscv_tprel_add", 0, 0, 0},
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{"fixup_riscv_tls_got_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_riscv_tls_gd_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_riscv_jal", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_riscv_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_riscv_rvc_jump", 2, 11, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_riscv_rvc_branch", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_riscv_call", 0, 64, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_riscv_call_plt", 0, 64, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_riscv_relax", 0, 0, 0},
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{"fixup_riscv_align", 0, 0, 0}};
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static_assert((array_lengthof(Infos)) == RISCV::NumTargetFixupKinds,
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"Not all fixup kinds added to Infos array");
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// Fixup kinds from .reloc directive are like R_RISCV_NONE. They
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// do not require any extra processing.
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if (Kind >= FirstLiteralRelocationKind)
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return MCAsmBackend::getFixupKindInfo(FK_NONE);
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if (Kind < FirstTargetFixupKind)
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return MCAsmBackend::getFixupKindInfo(Kind);
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assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
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"Invalid kind!");
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return Infos[Kind - FirstTargetFixupKind];
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}
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// If linker relaxation is enabled, or the relax option had previously been
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// enabled, always emit relocations even if the fixup can be resolved. This is
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// necessary for correctness as offsets may change during relaxation.
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bool RISCVAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
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const MCFixup &Fixup,
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const MCValue &Target) {
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if (Fixup.getKind() >= FirstLiteralRelocationKind)
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return true;
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switch (Fixup.getTargetKind()) {
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default:
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break;
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case FK_Data_1:
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case FK_Data_2:
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case FK_Data_4:
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case FK_Data_8:
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if (Target.isAbsolute())
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return false;
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break;
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case RISCV::fixup_riscv_got_hi20:
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case RISCV::fixup_riscv_tls_got_hi20:
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case RISCV::fixup_riscv_tls_gd_hi20:
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return true;
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}
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return STI.getFeatureBits()[RISCV::FeatureRelax] || ForceRelocs;
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}
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bool RISCVAsmBackend::fixupNeedsRelaxationAdvanced(const MCFixup &Fixup,
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bool Resolved,
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uint64_t Value,
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const MCRelaxableFragment *DF,
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const MCAsmLayout &Layout,
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const bool WasForced) const {
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// Return true if the symbol is actually unresolved.
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// Resolved could be always false when shouldForceRelocation return true.
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// We use !WasForced to indicate that the symbol is unresolved and not forced
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// by shouldForceRelocation.
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if (!Resolved && !WasForced)
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return true;
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int64_t Offset = int64_t(Value);
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switch (Fixup.getTargetKind()) {
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default:
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return false;
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case RISCV::fixup_riscv_rvc_branch:
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// For compressed branch instructions the immediate must be
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// in the range [-256, 254].
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return Offset > 254 || Offset < -256;
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case RISCV::fixup_riscv_rvc_jump:
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// For compressed jump instructions the immediate must be
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// in the range [-2048, 2046].
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return Offset > 2046 || Offset < -2048;
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}
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}
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void RISCVAsmBackend::relaxInstruction(MCInst &Inst,
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const MCSubtargetInfo &STI) const {
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// TODO: replace this with call to auto generated uncompressinstr() function.
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MCInst Res;
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switch (Inst.getOpcode()) {
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default:
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llvm_unreachable("Opcode not expected!");
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case RISCV::C_BEQZ:
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// c.beqz $rs1, $imm -> beq $rs1, X0, $imm.
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Res.setOpcode(RISCV::BEQ);
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Res.addOperand(Inst.getOperand(0));
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Res.addOperand(MCOperand::createReg(RISCV::X0));
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Res.addOperand(Inst.getOperand(1));
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break;
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case RISCV::C_BNEZ:
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// c.bnez $rs1, $imm -> bne $rs1, X0, $imm.
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Res.setOpcode(RISCV::BNE);
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Res.addOperand(Inst.getOperand(0));
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Res.addOperand(MCOperand::createReg(RISCV::X0));
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Res.addOperand(Inst.getOperand(1));
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break;
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case RISCV::C_J:
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// c.j $imm -> jal X0, $imm.
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Res.setOpcode(RISCV::JAL);
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Res.addOperand(MCOperand::createReg(RISCV::X0));
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Res.addOperand(Inst.getOperand(0));
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break;
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case RISCV::C_JAL:
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// c.jal $imm -> jal X1, $imm.
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Res.setOpcode(RISCV::JAL);
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Res.addOperand(MCOperand::createReg(RISCV::X1));
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Res.addOperand(Inst.getOperand(0));
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break;
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}
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Inst = std::move(Res);
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}
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// Given a compressed control flow instruction this function returns
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// the expanded instruction.
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unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const {
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switch (Op) {
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default:
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return Op;
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case RISCV::C_BEQZ:
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return RISCV::BEQ;
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case RISCV::C_BNEZ:
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return RISCV::BNE;
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case RISCV::C_J:
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case RISCV::C_JAL: // fall through.
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return RISCV::JAL;
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}
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}
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bool RISCVAsmBackend::mayNeedRelaxation(const MCInst &Inst,
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const MCSubtargetInfo &STI) const {
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return getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode();
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}
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bool RISCVAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
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bool HasStdExtC = STI.getFeatureBits()[RISCV::FeatureStdExtC];
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unsigned MinNopLen = HasStdExtC ? 2 : 4;
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if ((Count % MinNopLen) != 0)
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return false;
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// The canonical nop on RISC-V is addi x0, x0, 0.
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for (; Count >= 4; Count -= 4)
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OS.write("\x13\0\0\0", 4);
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// The canonical nop on RVC is c.nop.
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if (Count && HasStdExtC)
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OS.write("\x01\0", 2);
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return true;
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}
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static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
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MCContext &Ctx) {
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switch (Fixup.getTargetKind()) {
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default:
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llvm_unreachable("Unknown fixup kind!");
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case RISCV::fixup_riscv_got_hi20:
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case RISCV::fixup_riscv_tls_got_hi20:
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case RISCV::fixup_riscv_tls_gd_hi20:
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llvm_unreachable("Relocation should be unconditionally forced\n");
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case FK_Data_1:
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case FK_Data_2:
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case FK_Data_4:
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case FK_Data_8:
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case FK_Data_6b:
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return Value;
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case RISCV::fixup_riscv_lo12_i:
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case RISCV::fixup_riscv_pcrel_lo12_i:
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case RISCV::fixup_riscv_tprel_lo12_i:
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return Value & 0xfff;
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case RISCV::fixup_riscv_lo12_s:
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case RISCV::fixup_riscv_pcrel_lo12_s:
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case RISCV::fixup_riscv_tprel_lo12_s:
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return (((Value >> 5) & 0x7f) << 25) | ((Value & 0x1f) << 7);
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case RISCV::fixup_riscv_hi20:
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case RISCV::fixup_riscv_pcrel_hi20:
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case RISCV::fixup_riscv_tprel_hi20:
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// Add 1 if bit 11 is 1, to compensate for low 12 bits being negative.
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return ((Value + 0x800) >> 12) & 0xfffff;
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case RISCV::fixup_riscv_jal: {
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if (!isInt<21>(Value))
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Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
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if (Value & 0x1)
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Ctx.reportError(Fixup.getLoc(), "fixup value must be 2-byte aligned");
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// Need to produce imm[19|10:1|11|19:12] from the 21-bit Value.
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unsigned Sbit = (Value >> 20) & 0x1;
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unsigned Hi8 = (Value >> 12) & 0xff;
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unsigned Mid1 = (Value >> 11) & 0x1;
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unsigned Lo10 = (Value >> 1) & 0x3ff;
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// Inst{31} = Sbit;
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// Inst{30-21} = Lo10;
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// Inst{20} = Mid1;
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// Inst{19-12} = Hi8;
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Value = (Sbit << 19) | (Lo10 << 9) | (Mid1 << 8) | Hi8;
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return Value;
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}
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case RISCV::fixup_riscv_branch: {
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if (!isInt<13>(Value))
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Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
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if (Value & 0x1)
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Ctx.reportError(Fixup.getLoc(), "fixup value must be 2-byte aligned");
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// Need to extract imm[12], imm[10:5], imm[4:1], imm[11] from the 13-bit
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// Value.
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unsigned Sbit = (Value >> 12) & 0x1;
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unsigned Hi1 = (Value >> 11) & 0x1;
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unsigned Mid6 = (Value >> 5) & 0x3f;
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unsigned Lo4 = (Value >> 1) & 0xf;
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// Inst{31} = Sbit;
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// Inst{30-25} = Mid6;
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// Inst{11-8} = Lo4;
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// Inst{7} = Hi1;
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Value = (Sbit << 31) | (Mid6 << 25) | (Lo4 << 8) | (Hi1 << 7);
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return Value;
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}
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case RISCV::fixup_riscv_call:
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case RISCV::fixup_riscv_call_plt: {
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// Jalr will add UpperImm with the sign-extended 12-bit LowerImm,
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// we need to add 0x800ULL before extract upper bits to reflect the
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// effect of the sign extension.
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uint64_t UpperImm = (Value + 0x800ULL) & 0xfffff000ULL;
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uint64_t LowerImm = Value & 0xfffULL;
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return UpperImm | ((LowerImm << 20) << 32);
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}
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case RISCV::fixup_riscv_rvc_jump: {
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// Need to produce offset[11|4|9:8|10|6|7|3:1|5] from the 11-bit Value.
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unsigned Bit11 = (Value >> 11) & 0x1;
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unsigned Bit4 = (Value >> 4) & 0x1;
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unsigned Bit9_8 = (Value >> 8) & 0x3;
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unsigned Bit10 = (Value >> 10) & 0x1;
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unsigned Bit6 = (Value >> 6) & 0x1;
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unsigned Bit7 = (Value >> 7) & 0x1;
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unsigned Bit3_1 = (Value >> 1) & 0x7;
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unsigned Bit5 = (Value >> 5) & 0x1;
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Value = (Bit11 << 10) | (Bit4 << 9) | (Bit9_8 << 7) | (Bit10 << 6) |
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(Bit6 << 5) | (Bit7 << 4) | (Bit3_1 << 1) | Bit5;
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return Value;
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}
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case RISCV::fixup_riscv_rvc_branch: {
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// Need to produce offset[8|4:3], [reg 3 bit], offset[7:6|2:1|5]
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unsigned Bit8 = (Value >> 8) & 0x1;
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unsigned Bit7_6 = (Value >> 6) & 0x3;
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unsigned Bit5 = (Value >> 5) & 0x1;
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unsigned Bit4_3 = (Value >> 3) & 0x3;
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unsigned Bit2_1 = (Value >> 1) & 0x3;
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Value = (Bit8 << 12) | (Bit4_3 << 10) | (Bit7_6 << 5) | (Bit2_1 << 3) |
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(Bit5 << 2);
|
||
|
|
return Value;
|
||
|
|
}
|
||
|
|
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
bool RISCVAsmBackend::evaluateTargetFixup(
|
||
|
|
const MCAssembler &Asm, const MCAsmLayout &Layout, const MCFixup &Fixup,
|
||
|
|
const MCFragment *DF, const MCValue &Target, uint64_t &Value,
|
||
|
|
bool &WasForced) {
|
||
|
|
const MCFixup *AUIPCFixup;
|
||
|
|
const MCFragment *AUIPCDF;
|
||
|
|
MCValue AUIPCTarget;
|
||
|
|
switch (Fixup.getTargetKind()) {
|
||
|
|
default:
|
||
|
|
llvm_unreachable("Unexpected fixup kind!");
|
||
|
|
case RISCV::fixup_riscv_pcrel_hi20:
|
||
|
|
AUIPCFixup = &Fixup;
|
||
|
|
AUIPCDF = DF;
|
||
|
|
AUIPCTarget = Target;
|
||
|
|
break;
|
||
|
|
case RISCV::fixup_riscv_pcrel_lo12_i:
|
||
|
|
case RISCV::fixup_riscv_pcrel_lo12_s: {
|
||
|
|
AUIPCFixup = cast<RISCVMCExpr>(Fixup.getValue())->getPCRelHiFixup(&AUIPCDF);
|
||
|
|
if (!AUIPCFixup) {
|
||
|
|
Asm.getContext().reportError(Fixup.getLoc(),
|
||
|
|
"could not find corresponding %pcrel_hi");
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
// MCAssembler::evaluateFixup will emit an error for this case when it sees
|
||
|
|
// the %pcrel_hi, so don't duplicate it when also seeing the %pcrel_lo.
|
||
|
|
const MCExpr *AUIPCExpr = AUIPCFixup->getValue();
|
||
|
|
if (!AUIPCExpr->evaluateAsRelocatable(AUIPCTarget, &Layout, AUIPCFixup))
|
||
|
|
return true;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!AUIPCTarget.getSymA() || AUIPCTarget.getSymB())
|
||
|
|
return false;
|
||
|
|
|
||
|
|
const MCSymbolRefExpr *A = AUIPCTarget.getSymA();
|
||
|
|
const MCSymbol &SA = A->getSymbol();
|
||
|
|
if (A->getKind() != MCSymbolRefExpr::VK_None || SA.isUndefined())
|
||
|
|
return false;
|
||
|
|
|
||
|
|
auto *Writer = Asm.getWriterPtr();
|
||
|
|
if (!Writer)
|
||
|
|
return false;
|
||
|
|
|
||
|
|
bool IsResolved = Writer->isSymbolRefDifferenceFullyResolvedImpl(
|
||
|
|
Asm, SA, *AUIPCDF, false, true);
|
||
|
|
if (!IsResolved)
|
||
|
|
return false;
|
||
|
|
|
||
|
|
Value = Layout.getSymbolOffset(SA) + AUIPCTarget.getConstant();
|
||
|
|
Value -= Layout.getFragmentOffset(AUIPCDF) + AUIPCFixup->getOffset();
|
||
|
|
|
||
|
|
if (shouldForceRelocation(Asm, *AUIPCFixup, AUIPCTarget)) {
|
||
|
|
WasForced = true;
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
void RISCVAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
|
||
|
|
const MCValue &Target,
|
||
|
|
MutableArrayRef<char> Data, uint64_t Value,
|
||
|
|
bool IsResolved,
|
||
|
|
const MCSubtargetInfo *STI) const {
|
||
|
|
MCFixupKind Kind = Fixup.getKind();
|
||
|
|
if (Kind >= FirstLiteralRelocationKind)
|
||
|
|
return;
|
||
|
|
MCContext &Ctx = Asm.getContext();
|
||
|
|
MCFixupKindInfo Info = getFixupKindInfo(Kind);
|
||
|
|
if (!Value)
|
||
|
|
return; // Doesn't change encoding.
|
||
|
|
// Apply any target-specific value adjustments.
|
||
|
|
Value = adjustFixupValue(Fixup, Value, Ctx);
|
||
|
|
|
||
|
|
// Shift the value into position.
|
||
|
|
Value <<= Info.TargetOffset;
|
||
|
|
|
||
|
|
unsigned Offset = Fixup.getOffset();
|
||
|
|
unsigned NumBytes = alignTo(Info.TargetSize + Info.TargetOffset, 8) / 8;
|
||
|
|
|
||
|
|
assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
|
||
|
|
|
||
|
|
// For each byte of the fragment that the fixup touches, mask in the
|
||
|
|
// bits from the fixup value.
|
||
|
|
for (unsigned i = 0; i != NumBytes; ++i) {
|
||
|
|
Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
// Linker relaxation may change code size. We have to insert Nops
|
||
|
|
// for .align directive when linker relaxation enabled. So then Linker
|
||
|
|
// could satisfy alignment by removing Nops.
|
||
|
|
// The function return the total Nops Size we need to insert.
|
||
|
|
bool RISCVAsmBackend::shouldInsertExtraNopBytesForCodeAlign(
|
||
|
|
const MCAlignFragment &AF, unsigned &Size) {
|
||
|
|
// Calculate Nops Size only when linker relaxation enabled.
|
||
|
|
if (!STI.getFeatureBits()[RISCV::FeatureRelax])
|
||
|
|
return false;
|
||
|
|
|
||
|
|
bool HasStdExtC = STI.getFeatureBits()[RISCV::FeatureStdExtC];
|
||
|
|
unsigned MinNopLen = HasStdExtC ? 2 : 4;
|
||
|
|
|
||
|
|
if (AF.getAlignment() <= MinNopLen) {
|
||
|
|
return false;
|
||
|
|
} else {
|
||
|
|
Size = AF.getAlignment() - MinNopLen;
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
// We need to insert R_RISCV_ALIGN relocation type to indicate the
|
||
|
|
// position of Nops and the total bytes of the Nops have been inserted
|
||
|
|
// when linker relaxation enabled.
|
||
|
|
// The function insert fixup_riscv_align fixup which eventually will
|
||
|
|
// transfer to R_RISCV_ALIGN relocation type.
|
||
|
|
bool RISCVAsmBackend::shouldInsertFixupForCodeAlign(MCAssembler &Asm,
|
||
|
|
const MCAsmLayout &Layout,
|
||
|
|
MCAlignFragment &AF) {
|
||
|
|
// Insert the fixup only when linker relaxation enabled.
|
||
|
|
if (!STI.getFeatureBits()[RISCV::FeatureRelax])
|
||
|
|
return false;
|
||
|
|
|
||
|
|
// Calculate total Nops we need to insert. If there are none to insert
|
||
|
|
// then simply return.
|
||
|
|
unsigned Count;
|
||
|
|
if (!shouldInsertExtraNopBytesForCodeAlign(AF, Count) || (Count == 0))
|
||
|
|
return false;
|
||
|
|
|
||
|
|
MCContext &Ctx = Asm.getContext();
|
||
|
|
const MCExpr *Dummy = MCConstantExpr::create(0, Ctx);
|
||
|
|
// Create fixup_riscv_align fixup.
|
||
|
|
MCFixup Fixup =
|
||
|
|
MCFixup::create(0, Dummy, MCFixupKind(RISCV::fixup_riscv_align), SMLoc());
|
||
|
|
|
||
|
|
uint64_t FixedValue = 0;
|
||
|
|
MCValue NopBytes = MCValue::get(Count);
|
||
|
|
|
||
|
|
Asm.getWriter().recordRelocation(Asm, Layout, &AF, Fixup, NopBytes,
|
||
|
|
FixedValue);
|
||
|
|
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
std::unique_ptr<MCObjectTargetWriter>
|
||
|
|
RISCVAsmBackend::createObjectTargetWriter() const {
|
||
|
|
return createRISCVELFObjectWriter(OSABI, Is64Bit);
|
||
|
|
}
|
||
|
|
|
||
|
|
MCAsmBackend *llvm::createRISCVAsmBackend(const Target &T,
|
||
|
|
const MCSubtargetInfo &STI,
|
||
|
|
const MCRegisterInfo &MRI,
|
||
|
|
const MCTargetOptions &Options) {
|
||
|
|
const Triple &TT = STI.getTargetTriple();
|
||
|
|
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
|
||
|
|
return new RISCVAsmBackend(STI, OSABI, TT.isArch64Bit(), Options);
|
||
|
|
}
|