492 lines
18 KiB
C++
492 lines
18 KiB
C++
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//===------------- PPCExpandISEL.cpp - Expand ISEL instruction ------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// A pass that expands the ISEL instruction into an if-then-else sequence.
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// This pass must be run post-RA since all operands must be physical registers.
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//
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//===----------------------------------------------------------------------===//
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#include "PPC.h"
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#include "PPCInstrInfo.h"
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#include "PPCSubtarget.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/LivePhysRegs.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "ppc-expand-isel"
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STATISTIC(NumExpanded, "Number of ISEL instructions expanded");
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STATISTIC(NumRemoved, "Number of ISEL instructions removed");
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STATISTIC(NumFolded, "Number of ISEL instructions folded");
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// If -ppc-gen-isel=false is set, we will disable generating the ISEL
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// instruction on all PPC targets. Otherwise, if the user set option
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// -misel or the platform supports ISEL by default, still generate the
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// ISEL instruction, else expand it.
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static cl::opt<bool>
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GenerateISEL("ppc-gen-isel",
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cl::desc("Enable generating the ISEL instruction."),
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cl::init(true), cl::Hidden);
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namespace {
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class PPCExpandISEL : public MachineFunctionPass {
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DebugLoc dl;
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MachineFunction *MF;
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const TargetInstrInfo *TII;
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bool IsTrueBlockRequired;
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bool IsFalseBlockRequired;
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MachineBasicBlock *TrueBlock;
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MachineBasicBlock *FalseBlock;
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MachineBasicBlock *NewSuccessor;
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MachineBasicBlock::iterator TrueBlockI;
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MachineBasicBlock::iterator FalseBlockI;
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typedef SmallVector<MachineInstr *, 4> BlockISELList;
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typedef SmallDenseMap<int, BlockISELList> ISELInstructionList;
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// A map of MBB numbers to their lists of contained ISEL instructions.
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// Please note when we traverse this list and expand ISEL, we only remove
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// the ISEL from the MBB not from this list.
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ISELInstructionList ISELInstructions;
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/// Initialize the object.
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void initialize(MachineFunction &MFParam);
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void handleSpecialCases(BlockISELList &BIL, MachineBasicBlock *MBB);
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void reorganizeBlockLayout(BlockISELList &BIL, MachineBasicBlock *MBB);
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void populateBlocks(BlockISELList &BIL);
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void expandMergeableISELs(BlockISELList &BIL);
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void expandAndMergeISELs();
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bool canMerge(MachineInstr *PrevPushedMI, MachineInstr *MI);
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/// Is this instruction an ISEL or ISEL8?
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static bool isISEL(const MachineInstr &MI) {
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return (MI.getOpcode() == PPC::ISEL || MI.getOpcode() == PPC::ISEL8);
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}
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/// Is this instruction an ISEL8?
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static bool isISEL8(const MachineInstr &MI) {
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return (MI.getOpcode() == PPC::ISEL8);
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}
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/// Are the two operands using the same register?
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bool useSameRegister(const MachineOperand &Op1, const MachineOperand &Op2) {
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return (Op1.getReg() == Op2.getReg());
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}
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///
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/// Collect all ISEL instructions from the current function.
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///
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/// Walk the current function and collect all the ISEL instructions that are
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/// found. The instructions are placed in the ISELInstructions vector.
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///
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/// \return true if any ISEL instructions were found, false otherwise
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///
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bool collectISELInstructions();
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public:
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static char ID;
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PPCExpandISEL() : MachineFunctionPass(ID) {
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initializePPCExpandISELPass(*PassRegistry::getPassRegistry());
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}
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///
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/// Determine whether to generate the ISEL instruction or expand it.
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///
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/// Expand ISEL instruction into if-then-else sequence when one of
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/// the following two conditions hold:
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/// (1) -ppc-gen-isel=false
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/// (2) hasISEL() return false
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/// Otherwise, still generate ISEL instruction.
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/// The -ppc-gen-isel option is set to true by default. Which means the ISEL
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/// instruction is still generated by default on targets that support them.
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///
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/// \return true if ISEL should be expanded into if-then-else code sequence;
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/// false if ISEL instruction should be generated, i.e. not expanded.
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///
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static bool isExpandISELEnabled(const MachineFunction &MF);
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#ifndef NDEBUG
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void DumpISELInstructions() const;
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#endif
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bool runOnMachineFunction(MachineFunction &MF) override {
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LLVM_DEBUG(dbgs() << "Function: "; MF.dump(); dbgs() << "\n");
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initialize(MF);
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if (!collectISELInstructions()) {
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LLVM_DEBUG(dbgs() << "No ISEL instructions in this function\n");
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return false;
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}
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#ifndef NDEBUG
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DumpISELInstructions();
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#endif
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expandAndMergeISELs();
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return true;
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}
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};
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} // end anonymous namespace
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void PPCExpandISEL::initialize(MachineFunction &MFParam) {
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MF = &MFParam;
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TII = MF->getSubtarget().getInstrInfo();
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ISELInstructions.clear();
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}
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bool PPCExpandISEL::isExpandISELEnabled(const MachineFunction &MF) {
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return !GenerateISEL || !MF.getSubtarget<PPCSubtarget>().hasISEL();
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}
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bool PPCExpandISEL::collectISELInstructions() {
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for (MachineBasicBlock &MBB : *MF) {
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BlockISELList thisBlockISELs;
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for (MachineInstr &MI : MBB)
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if (isISEL(MI))
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thisBlockISELs.push_back(&MI);
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if (!thisBlockISELs.empty())
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ISELInstructions.insert(std::make_pair(MBB.getNumber(), thisBlockISELs));
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}
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return !ISELInstructions.empty();
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}
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#ifndef NDEBUG
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void PPCExpandISEL::DumpISELInstructions() const {
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for (const auto &I : ISELInstructions) {
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LLVM_DEBUG(dbgs() << printMBBReference(*MF->getBlockNumbered(I.first))
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<< ":\n");
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for (const auto &VI : I.second)
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LLVM_DEBUG(dbgs() << " "; VI->print(dbgs()));
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}
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}
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#endif
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/// Contiguous ISELs that have the same condition can be merged.
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bool PPCExpandISEL::canMerge(MachineInstr *PrevPushedMI, MachineInstr *MI) {
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// Same Condition Register?
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if (!useSameRegister(PrevPushedMI->getOperand(3), MI->getOperand(3)))
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return false;
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MachineBasicBlock::iterator PrevPushedMBBI = *PrevPushedMI;
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MachineBasicBlock::iterator MBBI = *MI;
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return (std::prev(MBBI) == PrevPushedMBBI); // Contiguous ISELs?
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}
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void PPCExpandISEL::expandAndMergeISELs() {
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bool ExpandISELEnabled = isExpandISELEnabled(*MF);
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for (auto &BlockList : ISELInstructions) {
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LLVM_DEBUG(
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dbgs() << "Expanding ISEL instructions in "
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<< printMBBReference(*MF->getBlockNumbered(BlockList.first))
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<< "\n");
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BlockISELList &CurrentISELList = BlockList.second;
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auto I = CurrentISELList.begin();
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auto E = CurrentISELList.end();
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while (I != E) {
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assert(isISEL(**I) && "Expecting an ISEL instruction");
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MachineOperand &Dest = (*I)->getOperand(0);
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MachineOperand &TrueValue = (*I)->getOperand(1);
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MachineOperand &FalseValue = (*I)->getOperand(2);
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// Special case 1, all registers used by ISEL are the same one.
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// The non-redundant isel 0, 0, 0, N would not satisfy these conditions
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// as it would be ISEL %R0, %ZERO, %R0, %CRN.
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if (useSameRegister(Dest, TrueValue) &&
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useSameRegister(Dest, FalseValue)) {
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LLVM_DEBUG(dbgs() << "Remove redundant ISEL instruction: " << **I
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<< "\n");
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// FIXME: if the CR field used has no other uses, we could eliminate the
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// instruction that defines it. This would have to be done manually
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// since this pass runs too late to run DCE after it.
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NumRemoved++;
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(*I)->eraseFromParent();
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I++;
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} else if (useSameRegister(TrueValue, FalseValue)) {
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// Special case 2, the two input registers used by ISEL are the same.
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// Note: the non-foldable isel RX, 0, 0, N would not satisfy this
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// condition as it would be ISEL %RX, %ZERO, %R0, %CRN, which makes it
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// safe to fold ISEL to MR(OR) instead of ADDI.
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MachineBasicBlock *MBB = (*I)->getParent();
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LLVM_DEBUG(
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dbgs() << "Fold the ISEL instruction to an unconditional copy:\n");
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LLVM_DEBUG(dbgs() << "ISEL: " << **I << "\n");
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NumFolded++;
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// Note: we're using both the TrueValue and FalseValue operands so as
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// not to lose the kill flag if it is set on either of them.
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BuildMI(*MBB, (*I), dl, TII->get(isISEL8(**I) ? PPC::OR8 : PPC::OR))
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.add(Dest)
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.add(TrueValue)
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.add(FalseValue);
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(*I)->eraseFromParent();
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I++;
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} else if (ExpandISELEnabled) { // Normal cases expansion enabled
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LLVM_DEBUG(dbgs() << "Expand ISEL instructions:\n");
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LLVM_DEBUG(dbgs() << "ISEL: " << **I << "\n");
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BlockISELList SubISELList;
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SubISELList.push_back(*I++);
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// Collect the ISELs that can be merged together.
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// This will eat up ISEL instructions without considering whether they
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// may be redundant or foldable to a register copy. So we still keep
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// the handleSpecialCases() downstream to handle them.
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while (I != E && canMerge(SubISELList.back(), *I)) {
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LLVM_DEBUG(dbgs() << "ISEL: " << **I << "\n");
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SubISELList.push_back(*I++);
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}
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expandMergeableISELs(SubISELList);
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} else { // Normal cases expansion disabled
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I++; // leave the ISEL as it is
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}
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} // end while
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} // end for
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}
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void PPCExpandISEL::handleSpecialCases(BlockISELList &BIL,
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MachineBasicBlock *MBB) {
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IsTrueBlockRequired = false;
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IsFalseBlockRequired = false;
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auto MI = BIL.begin();
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while (MI != BIL.end()) {
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assert(isISEL(**MI) && "Expecting an ISEL instruction");
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LLVM_DEBUG(dbgs() << "ISEL: " << **MI << "\n");
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MachineOperand &Dest = (*MI)->getOperand(0);
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MachineOperand &TrueValue = (*MI)->getOperand(1);
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MachineOperand &FalseValue = (*MI)->getOperand(2);
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// If at least one of the ISEL instructions satisfy the following
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// condition, we need the True Block:
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// The Dest Register and True Value Register are not the same
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// Similarly, if at least one of the ISEL instructions satisfy the
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// following condition, we need the False Block:
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// The Dest Register and False Value Register are not the same.
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bool IsADDIInstRequired = !useSameRegister(Dest, TrueValue);
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bool IsORIInstRequired = !useSameRegister(Dest, FalseValue);
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// Special case 1, all registers used by ISEL are the same one.
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if (!IsADDIInstRequired && !IsORIInstRequired) {
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LLVM_DEBUG(dbgs() << "Remove redundant ISEL instruction.");
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// FIXME: if the CR field used has no other uses, we could eliminate the
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// instruction that defines it. This would have to be done manually
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// since this pass runs too late to run DCE after it.
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NumRemoved++;
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(*MI)->eraseFromParent();
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// Setting MI to the erase result keeps the iterator valid and increased.
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MI = BIL.erase(MI);
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continue;
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}
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// Special case 2, the two input registers used by ISEL are the same.
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// Note 1: We favor merging ISEL expansions over folding a single one. If
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// the passed list has multiple merge-able ISEL's, we won't fold any.
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// Note 2: There is no need to test for PPC::R0/PPC::X0 because PPC::ZERO/
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// PPC::ZERO8 will be used for the first operand if the value is meant to
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// be zero. In this case, the useSameRegister method will return false,
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// thereby preventing this ISEL from being folded.
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if (useSameRegister(TrueValue, FalseValue) && (BIL.size() == 1)) {
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LLVM_DEBUG(
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dbgs() << "Fold the ISEL instruction to an unconditional copy.");
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NumFolded++;
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// Note: we're using both the TrueValue and FalseValue operands so as
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// not to lose the kill flag if it is set on either of them.
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BuildMI(*MBB, (*MI), dl, TII->get(isISEL8(**MI) ? PPC::OR8 : PPC::OR))
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.add(Dest)
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.add(TrueValue)
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.add(FalseValue);
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(*MI)->eraseFromParent();
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// Setting MI to the erase result keeps the iterator valid and increased.
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MI = BIL.erase(MI);
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continue;
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}
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IsTrueBlockRequired |= IsADDIInstRequired;
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IsFalseBlockRequired |= IsORIInstRequired;
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MI++;
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}
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}
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void PPCExpandISEL::reorganizeBlockLayout(BlockISELList &BIL,
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MachineBasicBlock *MBB) {
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if (BIL.empty())
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return;
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assert((IsTrueBlockRequired || IsFalseBlockRequired) &&
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"Should have been handled by special cases earlier!");
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MachineBasicBlock *Successor = nullptr;
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const BasicBlock *LLVM_BB = MBB->getBasicBlock();
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MachineBasicBlock::iterator MBBI = (*BIL.back());
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NewSuccessor = (MBBI != MBB->getLastNonDebugInstr() || !MBB->canFallThrough())
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// Another BB is needed to move the instructions that
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// follow this ISEL. If the ISEL is the last instruction
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// in a block that can't fall through, we also need a block
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// to branch to.
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? MF->CreateMachineBasicBlock(LLVM_BB)
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: nullptr;
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MachineFunction::iterator It = MBB->getIterator();
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++It; // Point to the successor block of MBB.
|
||
|
|
|
||
|
|
// If NewSuccessor is NULL then the last ISEL in this group is the last
|
||
|
|
// non-debug instruction in this block. Find the fall-through successor
|
||
|
|
// of this block to use when updating the CFG below.
|
||
|
|
if (!NewSuccessor) {
|
||
|
|
for (auto &Succ : MBB->successors()) {
|
||
|
|
if (MBB->isLayoutSuccessor(Succ)) {
|
||
|
|
Successor = Succ;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
} else
|
||
|
|
Successor = NewSuccessor;
|
||
|
|
|
||
|
|
// The FalseBlock and TrueBlock are inserted after the MBB block but before
|
||
|
|
// its successor.
|
||
|
|
// Note this need to be done *after* the above setting the Successor code.
|
||
|
|
if (IsFalseBlockRequired) {
|
||
|
|
FalseBlock = MF->CreateMachineBasicBlock(LLVM_BB);
|
||
|
|
MF->insert(It, FalseBlock);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (IsTrueBlockRequired) {
|
||
|
|
TrueBlock = MF->CreateMachineBasicBlock(LLVM_BB);
|
||
|
|
MF->insert(It, TrueBlock);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (NewSuccessor) {
|
||
|
|
MF->insert(It, NewSuccessor);
|
||
|
|
|
||
|
|
// Transfer the rest of this block into the new successor block.
|
||
|
|
NewSuccessor->splice(NewSuccessor->end(), MBB,
|
||
|
|
std::next(MachineBasicBlock::iterator(BIL.back())),
|
||
|
|
MBB->end());
|
||
|
|
NewSuccessor->transferSuccessorsAndUpdatePHIs(MBB);
|
||
|
|
|
||
|
|
// Update the liveins for NewSuccessor.
|
||
|
|
LivePhysRegs LPR;
|
||
|
|
computeAndAddLiveIns(LPR, *NewSuccessor);
|
||
|
|
|
||
|
|
} else {
|
||
|
|
// Remove successor from MBB.
|
||
|
|
MBB->removeSuccessor(Successor);
|
||
|
|
}
|
||
|
|
|
||
|
|
// Note that this needs to be done *after* transfering the successors from MBB
|
||
|
|
// to the NewSuccessor block, otherwise these blocks will also be transferred
|
||
|
|
// as successors!
|
||
|
|
MBB->addSuccessor(IsTrueBlockRequired ? TrueBlock : Successor);
|
||
|
|
MBB->addSuccessor(IsFalseBlockRequired ? FalseBlock : Successor);
|
||
|
|
|
||
|
|
if (IsTrueBlockRequired) {
|
||
|
|
TrueBlockI = TrueBlock->begin();
|
||
|
|
TrueBlock->addSuccessor(Successor);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (IsFalseBlockRequired) {
|
||
|
|
FalseBlockI = FalseBlock->begin();
|
||
|
|
FalseBlock->addSuccessor(Successor);
|
||
|
|
}
|
||
|
|
|
||
|
|
// Conditional branch to the TrueBlock or Successor
|
||
|
|
BuildMI(*MBB, BIL.back(), dl, TII->get(PPC::BC))
|
||
|
|
.add(BIL.back()->getOperand(3))
|
||
|
|
.addMBB(IsTrueBlockRequired ? TrueBlock : Successor);
|
||
|
|
|
||
|
|
// Jump over the true block to the new successor if the condition is false.
|
||
|
|
BuildMI(*(IsFalseBlockRequired ? FalseBlock : MBB),
|
||
|
|
(IsFalseBlockRequired ? FalseBlockI : BIL.back()), dl,
|
||
|
|
TII->get(PPC::B))
|
||
|
|
.addMBB(Successor);
|
||
|
|
|
||
|
|
if (IsFalseBlockRequired)
|
||
|
|
FalseBlockI = FalseBlock->begin(); // get the position of PPC::B
|
||
|
|
}
|
||
|
|
|
||
|
|
void PPCExpandISEL::populateBlocks(BlockISELList &BIL) {
|
||
|
|
for (auto &MI : BIL) {
|
||
|
|
assert(isISEL(*MI) && "Expecting an ISEL instruction");
|
||
|
|
|
||
|
|
MachineOperand &Dest = MI->getOperand(0); // location to store to
|
||
|
|
MachineOperand &TrueValue = MI->getOperand(1); // Value to store if
|
||
|
|
// condition is true
|
||
|
|
MachineOperand &FalseValue = MI->getOperand(2); // Value to store if
|
||
|
|
// condition is false
|
||
|
|
|
||
|
|
LLVM_DEBUG(dbgs() << "Dest: " << Dest << "\n");
|
||
|
|
LLVM_DEBUG(dbgs() << "TrueValue: " << TrueValue << "\n");
|
||
|
|
LLVM_DEBUG(dbgs() << "FalseValue: " << FalseValue << "\n");
|
||
|
|
LLVM_DEBUG(dbgs() << "ConditionRegister: " << MI->getOperand(3) << "\n");
|
||
|
|
|
||
|
|
// If the Dest Register and True Value Register are not the same one, we
|
||
|
|
// need the True Block.
|
||
|
|
bool IsADDIInstRequired = !useSameRegister(Dest, TrueValue);
|
||
|
|
bool IsORIInstRequired = !useSameRegister(Dest, FalseValue);
|
||
|
|
|
||
|
|
// Copy the result into the destination if the condition is true.
|
||
|
|
if (IsADDIInstRequired)
|
||
|
|
BuildMI(*TrueBlock, TrueBlockI, dl,
|
||
|
|
TII->get(isISEL8(*MI) ? PPC::ADDI8 : PPC::ADDI))
|
||
|
|
.add(Dest)
|
||
|
|
.add(TrueValue)
|
||
|
|
.add(MachineOperand::CreateImm(0));
|
||
|
|
|
||
|
|
// Copy the result into the destination if the condition is false.
|
||
|
|
if (IsORIInstRequired)
|
||
|
|
BuildMI(*FalseBlock, FalseBlockI, dl,
|
||
|
|
TII->get(isISEL8(*MI) ? PPC::ORI8 : PPC::ORI))
|
||
|
|
.add(Dest)
|
||
|
|
.add(FalseValue)
|
||
|
|
.add(MachineOperand::CreateImm(0));
|
||
|
|
|
||
|
|
MI->eraseFromParent(); // Remove the ISEL instruction.
|
||
|
|
|
||
|
|
NumExpanded++;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (IsTrueBlockRequired) {
|
||
|
|
// Update the liveins for TrueBlock.
|
||
|
|
LivePhysRegs LPR;
|
||
|
|
computeAndAddLiveIns(LPR, *TrueBlock);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (IsFalseBlockRequired) {
|
||
|
|
// Update the liveins for FalseBlock.
|
||
|
|
LivePhysRegs LPR;
|
||
|
|
computeAndAddLiveIns(LPR, *FalseBlock);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
void PPCExpandISEL::expandMergeableISELs(BlockISELList &BIL) {
|
||
|
|
// At this stage all the ISELs of BIL are in the same MBB.
|
||
|
|
MachineBasicBlock *MBB = BIL.back()->getParent();
|
||
|
|
|
||
|
|
handleSpecialCases(BIL, MBB);
|
||
|
|
reorganizeBlockLayout(BIL, MBB);
|
||
|
|
populateBlocks(BIL);
|
||
|
|
}
|
||
|
|
|
||
|
|
INITIALIZE_PASS(PPCExpandISEL, DEBUG_TYPE, "PowerPC Expand ISEL Generation",
|
||
|
|
false, false)
|
||
|
|
char PPCExpandISEL::ID = 0;
|
||
|
|
|
||
|
|
FunctionPass *llvm::createPPCExpandISELPass() { return new PPCExpandISEL(); }
|