59 lines
1.8 KiB
TableGen
59 lines
1.8 KiB
TableGen
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//===- NVPTXInstrFormats.td - NVPTX Instruction Formats-------*- tblgen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Describe NVPTX instructions format
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//
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//===----------------------------------------------------------------------===//
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// Vector instruction type enum
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class VecInstTypeEnum<bits<4> val> {
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bits<4> Value=val;
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}
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def VecNOP : VecInstTypeEnum<0>;
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// Generic NVPTX Format
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class NVPTXInst<dag outs, dag ins, string asmstr, list<dag> pattern>
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: Instruction {
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field bits<14> Inst;
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let Namespace = "NVPTX";
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dag OutOperandList = outs;
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dag InOperandList = ins;
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let AsmString = asmstr;
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let Pattern = pattern;
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// TSFlagFields
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bits<4> VecInstType = VecNOP.Value;
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bit IsSimpleMove = false;
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bit IsLoad = false;
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bit IsStore = false;
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bit IsTex = false;
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bit IsSust = false;
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bit IsSurfTexQuery = false;
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bit IsTexModeUnified = false;
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// The following field is encoded as log2 of the vector size minus one,
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// with 0 meaning the operation is not a surface instruction. For example,
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// if IsSuld == 2, then the instruction is a suld instruction with vector size
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// 2**(2-1) = 2.
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bits<2> IsSuld = 0;
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let TSFlags{3...0} = VecInstType;
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let TSFlags{4...4} = IsSimpleMove;
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let TSFlags{5...5} = IsLoad;
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let TSFlags{6...6} = IsStore;
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let TSFlags{7} = IsTex;
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let TSFlags{9...8} = IsSuld;
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let TSFlags{10} = IsSust;
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let TSFlags{11} = IsSurfTexQuery;
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let TSFlags{12} = IsTexModeUnified;
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}
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