511 lines
15 KiB
C++
511 lines
15 KiB
C++
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//===-- BPFAsmParser.cpp - Parse BPF assembly to MCInst instructions --===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/BPFMCTargetDesc.h"
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#include "TargetInfo/BPFTargetInfo.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCParser/MCAsmLexer.h"
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#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
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#include "llvm/MC/MCParser/MCTargetAsmParser.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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namespace {
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struct BPFOperand;
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class BPFAsmParser : public MCTargetAsmParser {
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SMLoc getLoc() const { return getParser().getTok().getLoc(); }
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bool PreMatchCheck(OperandVector &Operands);
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bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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OperandVector &Operands, MCStreamer &Out,
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uint64_t &ErrorInfo,
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bool MatchingInlineAsm) override;
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bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
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OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
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SMLoc &EndLoc) override;
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bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
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SMLoc NameLoc, OperandVector &Operands) override;
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bool ParseDirective(AsmToken DirectiveID) override;
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// "=" is used as assignment operator for assembly statment, so can't be used
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// for symbol assignment.
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bool equalIsAsmAssignment() override { return false; }
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// "*" is used for dereferencing memory that it will be the start of
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// statement.
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bool starIsStartOfStatement() override { return true; }
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#define GET_ASSEMBLER_HEADER
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#include "BPFGenAsmMatcher.inc"
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OperandMatchResultTy parseImmediate(OperandVector &Operands);
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OperandMatchResultTy parseRegister(OperandVector &Operands);
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OperandMatchResultTy parseOperandAsOperator(OperandVector &Operands);
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public:
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enum BPFMatchResultTy {
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Match_Dummy = FIRST_TARGET_MATCH_RESULT_TY,
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#define GET_OPERAND_DIAGNOSTIC_TYPES
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#include "BPFGenAsmMatcher.inc"
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#undef GET_OPERAND_DIAGNOSTIC_TYPES
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};
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BPFAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
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const MCInstrInfo &MII, const MCTargetOptions &Options)
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: MCTargetAsmParser(Options, STI, MII) {
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setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
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}
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};
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/// BPFOperand - Instances of this class represent a parsed machine
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/// instruction
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struct BPFOperand : public MCParsedAsmOperand {
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enum KindTy {
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Token,
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Register,
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Immediate,
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} Kind;
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struct RegOp {
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unsigned RegNum;
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};
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struct ImmOp {
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const MCExpr *Val;
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};
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SMLoc StartLoc, EndLoc;
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union {
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StringRef Tok;
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RegOp Reg;
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ImmOp Imm;
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};
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BPFOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
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public:
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BPFOperand(const BPFOperand &o) : MCParsedAsmOperand() {
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Kind = o.Kind;
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StartLoc = o.StartLoc;
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EndLoc = o.EndLoc;
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switch (Kind) {
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case Register:
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Reg = o.Reg;
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break;
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case Immediate:
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Imm = o.Imm;
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break;
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case Token:
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Tok = o.Tok;
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break;
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}
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}
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bool isToken() const override { return Kind == Token; }
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bool isReg() const override { return Kind == Register; }
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bool isImm() const override { return Kind == Immediate; }
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bool isMem() const override { return false; }
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bool isConstantImm() const {
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return isImm() && isa<MCConstantExpr>(getImm());
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}
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int64_t getConstantImm() const {
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const MCExpr *Val = getImm();
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return static_cast<const MCConstantExpr *>(Val)->getValue();
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}
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bool isSImm12() const {
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return (isConstantImm() && isInt<12>(getConstantImm()));
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}
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/// getStartLoc - Gets location of the first token of this operand
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SMLoc getStartLoc() const override { return StartLoc; }
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/// getEndLoc - Gets location of the last token of this operand
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SMLoc getEndLoc() const override { return EndLoc; }
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unsigned getReg() const override {
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assert(Kind == Register && "Invalid type access!");
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return Reg.RegNum;
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}
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const MCExpr *getImm() const {
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assert(Kind == Immediate && "Invalid type access!");
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return Imm.Val;
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}
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StringRef getToken() const {
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assert(Kind == Token && "Invalid type access!");
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return Tok;
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}
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void print(raw_ostream &OS) const override {
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switch (Kind) {
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case Immediate:
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OS << *getImm();
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break;
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case Register:
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OS << "<register x";
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OS << getReg() << ">";
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break;
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case Token:
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OS << "'" << getToken() << "'";
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break;
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}
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}
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void addExpr(MCInst &Inst, const MCExpr *Expr) const {
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assert(Expr && "Expr shouldn't be null!");
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if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
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Inst.addOperand(MCOperand::createImm(CE->getValue()));
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else
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Inst.addOperand(MCOperand::createExpr(Expr));
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}
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// Used by the TableGen Code
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void addRegOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::createReg(getReg()));
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}
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void addImmOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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addExpr(Inst, getImm());
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}
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static std::unique_ptr<BPFOperand> createToken(StringRef Str, SMLoc S) {
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auto Op = std::make_unique<BPFOperand>(Token);
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Op->Tok = Str;
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Op->StartLoc = S;
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Op->EndLoc = S;
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return Op;
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}
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static std::unique_ptr<BPFOperand> createReg(unsigned RegNo, SMLoc S,
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SMLoc E) {
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auto Op = std::make_unique<BPFOperand>(Register);
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Op->Reg.RegNum = RegNo;
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Op->StartLoc = S;
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Op->EndLoc = E;
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return Op;
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}
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static std::unique_ptr<BPFOperand> createImm(const MCExpr *Val, SMLoc S,
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SMLoc E) {
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auto Op = std::make_unique<BPFOperand>(Immediate);
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Op->Imm.Val = Val;
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Op->StartLoc = S;
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Op->EndLoc = E;
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return Op;
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}
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// Identifiers that can be used at the start of a statment.
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static bool isValidIdAtStart(StringRef Name) {
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return StringSwitch<bool>(Name.lower())
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.Case("if", true)
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.Case("call", true)
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.Case("goto", true)
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.Case("*", true)
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.Case("exit", true)
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.Case("lock", true)
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.Case("ld_pseudo", true)
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.Default(false);
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}
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// Identifiers that can be used in the middle of a statment.
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static bool isValidIdInMiddle(StringRef Name) {
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return StringSwitch<bool>(Name.lower())
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.Case("u64", true)
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.Case("u32", true)
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.Case("u16", true)
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.Case("u8", true)
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.Case("be64", true)
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.Case("be32", true)
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.Case("be16", true)
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.Case("le64", true)
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.Case("le32", true)
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.Case("le16", true)
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.Case("goto", true)
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.Case("ll", true)
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.Case("skb", true)
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.Case("s", true)
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.Default(false);
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}
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};
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} // end anonymous namespace.
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#define GET_REGISTER_MATCHER
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#define GET_MATCHER_IMPLEMENTATION
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#include "BPFGenAsmMatcher.inc"
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bool BPFAsmParser::PreMatchCheck(OperandVector &Operands) {
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if (Operands.size() == 4) {
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// check "reg1 = -reg2" and "reg1 = be16/be32/be64/le16/le32/le64 reg2",
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// reg1 must be the same as reg2
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BPFOperand &Op0 = (BPFOperand &)*Operands[0];
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BPFOperand &Op1 = (BPFOperand &)*Operands[1];
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BPFOperand &Op2 = (BPFOperand &)*Operands[2];
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BPFOperand &Op3 = (BPFOperand &)*Operands[3];
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if (Op0.isReg() && Op1.isToken() && Op2.isToken() && Op3.isReg()
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&& Op1.getToken() == "="
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&& (Op2.getToken() == "-" || Op2.getToken() == "be16"
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|| Op2.getToken() == "be32" || Op2.getToken() == "be64"
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|| Op2.getToken() == "le16" || Op2.getToken() == "le32"
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|| Op2.getToken() == "le64")
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&& Op0.getReg() != Op3.getReg())
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return true;
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}
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return false;
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}
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bool BPFAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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OperandVector &Operands,
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MCStreamer &Out, uint64_t &ErrorInfo,
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bool MatchingInlineAsm) {
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MCInst Inst;
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SMLoc ErrorLoc;
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if (PreMatchCheck(Operands))
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return Error(IDLoc, "additional inst constraint not met");
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switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
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default:
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break;
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case Match_Success:
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Inst.setLoc(IDLoc);
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Out.emitInstruction(Inst, getSTI());
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return false;
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case Match_MissingFeature:
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return Error(IDLoc, "instruction use requires an option to be enabled");
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case Match_MnemonicFail:
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return Error(IDLoc, "unrecognized instruction mnemonic");
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case Match_InvalidOperand:
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ErrorLoc = IDLoc;
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if (ErrorInfo != ~0U) {
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if (ErrorInfo >= Operands.size())
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return Error(ErrorLoc, "too few operands for instruction");
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ErrorLoc = ((BPFOperand &)*Operands[ErrorInfo]).getStartLoc();
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if (ErrorLoc == SMLoc())
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ErrorLoc = IDLoc;
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}
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return Error(ErrorLoc, "invalid operand for instruction");
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}
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llvm_unreachable("Unknown match type detected!");
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}
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bool BPFAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
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SMLoc &EndLoc) {
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if (tryParseRegister(RegNo, StartLoc, EndLoc) != MatchOperand_Success)
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return Error(StartLoc, "invalid register name");
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return false;
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}
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OperandMatchResultTy BPFAsmParser::tryParseRegister(unsigned &RegNo,
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SMLoc &StartLoc,
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SMLoc &EndLoc) {
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const AsmToken &Tok = getParser().getTok();
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StartLoc = Tok.getLoc();
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EndLoc = Tok.getEndLoc();
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RegNo = 0;
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StringRef Name = getLexer().getTok().getIdentifier();
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if (!MatchRegisterName(Name)) {
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getParser().Lex(); // Eat identifier token.
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return MatchOperand_Success;
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}
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return MatchOperand_NoMatch;
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}
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OperandMatchResultTy
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BPFAsmParser::parseOperandAsOperator(OperandVector &Operands) {
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SMLoc S = getLoc();
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if (getLexer().getKind() == AsmToken::Identifier) {
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StringRef Name = getLexer().getTok().getIdentifier();
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if (BPFOperand::isValidIdInMiddle(Name)) {
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getLexer().Lex();
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Operands.push_back(BPFOperand::createToken(Name, S));
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return MatchOperand_Success;
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}
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return MatchOperand_NoMatch;
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}
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switch (getLexer().getKind()) {
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case AsmToken::Minus:
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case AsmToken::Plus: {
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if (getLexer().peekTok().is(AsmToken::Integer))
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return MatchOperand_NoMatch;
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LLVM_FALLTHROUGH;
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}
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case AsmToken::Equal:
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case AsmToken::Greater:
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case AsmToken::Less:
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case AsmToken::Pipe:
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case AsmToken::Star:
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case AsmToken::LParen:
|
||
|
|
case AsmToken::RParen:
|
||
|
|
case AsmToken::LBrac:
|
||
|
|
case AsmToken::RBrac:
|
||
|
|
case AsmToken::Slash:
|
||
|
|
case AsmToken::Amp:
|
||
|
|
case AsmToken::Percent:
|
||
|
|
case AsmToken::Caret: {
|
||
|
|
StringRef Name = getLexer().getTok().getString();
|
||
|
|
getLexer().Lex();
|
||
|
|
Operands.push_back(BPFOperand::createToken(Name, S));
|
||
|
|
|
||
|
|
return MatchOperand_Success;
|
||
|
|
}
|
||
|
|
|
||
|
|
case AsmToken::EqualEqual:
|
||
|
|
case AsmToken::ExclaimEqual:
|
||
|
|
case AsmToken::GreaterEqual:
|
||
|
|
case AsmToken::GreaterGreater:
|
||
|
|
case AsmToken::LessEqual:
|
||
|
|
case AsmToken::LessLess: {
|
||
|
|
Operands.push_back(BPFOperand::createToken(
|
||
|
|
getLexer().getTok().getString().substr(0, 1), S));
|
||
|
|
Operands.push_back(BPFOperand::createToken(
|
||
|
|
getLexer().getTok().getString().substr(1, 1), S));
|
||
|
|
getLexer().Lex();
|
||
|
|
|
||
|
|
return MatchOperand_Success;
|
||
|
|
}
|
||
|
|
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
return MatchOperand_NoMatch;
|
||
|
|
}
|
||
|
|
|
||
|
|
OperandMatchResultTy BPFAsmParser::parseRegister(OperandVector &Operands) {
|
||
|
|
SMLoc S = getLoc();
|
||
|
|
SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1);
|
||
|
|
|
||
|
|
switch (getLexer().getKind()) {
|
||
|
|
default:
|
||
|
|
return MatchOperand_NoMatch;
|
||
|
|
case AsmToken::Identifier:
|
||
|
|
StringRef Name = getLexer().getTok().getIdentifier();
|
||
|
|
unsigned RegNo = MatchRegisterName(Name);
|
||
|
|
|
||
|
|
if (RegNo == 0)
|
||
|
|
return MatchOperand_NoMatch;
|
||
|
|
|
||
|
|
getLexer().Lex();
|
||
|
|
Operands.push_back(BPFOperand::createReg(RegNo, S, E));
|
||
|
|
}
|
||
|
|
return MatchOperand_Success;
|
||
|
|
}
|
||
|
|
|
||
|
|
OperandMatchResultTy BPFAsmParser::parseImmediate(OperandVector &Operands) {
|
||
|
|
switch (getLexer().getKind()) {
|
||
|
|
default:
|
||
|
|
return MatchOperand_NoMatch;
|
||
|
|
case AsmToken::LParen:
|
||
|
|
case AsmToken::Minus:
|
||
|
|
case AsmToken::Plus:
|
||
|
|
case AsmToken::Integer:
|
||
|
|
case AsmToken::String:
|
||
|
|
case AsmToken::Identifier:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
const MCExpr *IdVal;
|
||
|
|
SMLoc S = getLoc();
|
||
|
|
|
||
|
|
if (getParser().parseExpression(IdVal))
|
||
|
|
return MatchOperand_ParseFail;
|
||
|
|
|
||
|
|
SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1);
|
||
|
|
Operands.push_back(BPFOperand::createImm(IdVal, S, E));
|
||
|
|
|
||
|
|
return MatchOperand_Success;
|
||
|
|
}
|
||
|
|
|
||
|
|
/// ParseInstruction - Parse an BPF instruction which is in BPF verifier
|
||
|
|
/// format.
|
||
|
|
bool BPFAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
|
||
|
|
SMLoc NameLoc, OperandVector &Operands) {
|
||
|
|
// The first operand could be either register or actually an operator.
|
||
|
|
unsigned RegNo = MatchRegisterName(Name);
|
||
|
|
|
||
|
|
if (RegNo != 0) {
|
||
|
|
SMLoc E = SMLoc::getFromPointer(NameLoc.getPointer() - 1);
|
||
|
|
Operands.push_back(BPFOperand::createReg(RegNo, NameLoc, E));
|
||
|
|
} else if (BPFOperand::isValidIdAtStart (Name))
|
||
|
|
Operands.push_back(BPFOperand::createToken(Name, NameLoc));
|
||
|
|
else
|
||
|
|
return Error(NameLoc, "invalid register/token name");
|
||
|
|
|
||
|
|
while (!getLexer().is(AsmToken::EndOfStatement)) {
|
||
|
|
// Attempt to parse token as operator
|
||
|
|
if (parseOperandAsOperator(Operands) == MatchOperand_Success)
|
||
|
|
continue;
|
||
|
|
|
||
|
|
// Attempt to parse token as register
|
||
|
|
if (parseRegister(Operands) == MatchOperand_Success)
|
||
|
|
continue;
|
||
|
|
|
||
|
|
// Attempt to parse token as an immediate
|
||
|
|
if (parseImmediate(Operands) != MatchOperand_Success) {
|
||
|
|
SMLoc Loc = getLexer().getLoc();
|
||
|
|
return Error(Loc, "unexpected token");
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (getLexer().isNot(AsmToken::EndOfStatement)) {
|
||
|
|
SMLoc Loc = getLexer().getLoc();
|
||
|
|
|
||
|
|
getParser().eatToEndOfStatement();
|
||
|
|
|
||
|
|
return Error(Loc, "unexpected token");
|
||
|
|
}
|
||
|
|
|
||
|
|
// Consume the EndOfStatement.
|
||
|
|
getParser().Lex();
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
bool BPFAsmParser::ParseDirective(AsmToken DirectiveID) { return true; }
|
||
|
|
|
||
|
|
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeBPFAsmParser() {
|
||
|
|
RegisterMCAsmParser<BPFAsmParser> X(getTheBPFTarget());
|
||
|
|
RegisterMCAsmParser<BPFAsmParser> Y(getTheBPFleTarget());
|
||
|
|
RegisterMCAsmParser<BPFAsmParser> Z(getTheBPFbeTarget());
|
||
|
|
}
|