443 lines
15 KiB
C++
443 lines
15 KiB
C++
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//===- ARCInstrInfo.cpp - ARC Instruction Information -----------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the ARC implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "ARCInstrInfo.h"
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#include "ARC.h"
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#include "ARCMachineFunctionInfo.h"
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#include "ARCSubtarget.h"
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#include "MCTargetDesc/ARCInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define GET_INSTRINFO_CTOR_DTOR
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#include "ARCGenInstrInfo.inc"
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#define DEBUG_TYPE "arc-inst-info"
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enum AddrIncType {
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NoAddInc = 0,
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PreInc = 1,
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PostInc = 2,
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Scaled = 3
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};
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enum TSFlagsConstants {
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TSF_AddrModeOff = 0,
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TSF_AddModeMask = 3
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};
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// Pin the vtable to this file.
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void ARCInstrInfo::anchor() {}
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ARCInstrInfo::ARCInstrInfo()
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: ARCGenInstrInfo(ARC::ADJCALLSTACKDOWN, ARC::ADJCALLSTACKUP), RI() {}
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static bool isZeroImm(const MachineOperand &Op) {
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return Op.isImm() && Op.getImm() == 0;
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}
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static bool isLoad(int Opcode) {
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return Opcode == ARC::LD_rs9 || Opcode == ARC::LDH_rs9 ||
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Opcode == ARC::LDB_rs9;
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}
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static bool isStore(int Opcode) {
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return Opcode == ARC::ST_rs9 || Opcode == ARC::STH_rs9 ||
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Opcode == ARC::STB_rs9;
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}
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/// If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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unsigned ARCInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
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int &FrameIndex) const {
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int Opcode = MI.getOpcode();
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if (isLoad(Opcode)) {
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if ((MI.getOperand(1).isFI()) && // is a stack slot
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(MI.getOperand(2).isImm()) && // the imm is zero
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(isZeroImm(MI.getOperand(2)))) {
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FrameIndex = MI.getOperand(1).getIndex();
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return MI.getOperand(0).getReg();
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}
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}
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return 0;
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}
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/// If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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unsigned ARCInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
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int &FrameIndex) const {
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int Opcode = MI.getOpcode();
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if (isStore(Opcode)) {
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if ((MI.getOperand(1).isFI()) && // is a stack slot
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(MI.getOperand(2).isImm()) && // the imm is zero
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(isZeroImm(MI.getOperand(2)))) {
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FrameIndex = MI.getOperand(1).getIndex();
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return MI.getOperand(0).getReg();
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}
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}
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return 0;
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}
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/// Return the inverse of passed condition, i.e. turning COND_E to COND_NE.
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static ARCCC::CondCode GetOppositeBranchCondition(ARCCC::CondCode CC) {
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switch (CC) {
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default:
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llvm_unreachable("Illegal condition code!");
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case ARCCC::EQ:
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return ARCCC::NE;
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case ARCCC::NE:
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return ARCCC::EQ;
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case ARCCC::LO:
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return ARCCC::HS;
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case ARCCC::HS:
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return ARCCC::LO;
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case ARCCC::GT:
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return ARCCC::LE;
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case ARCCC::GE:
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return ARCCC::LT;
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case ARCCC::VS:
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return ARCCC::VC;
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case ARCCC::VC:
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return ARCCC::VS;
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case ARCCC::LT:
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return ARCCC::GE;
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case ARCCC::LE:
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return ARCCC::GT;
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case ARCCC::HI:
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return ARCCC::LS;
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case ARCCC::LS:
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return ARCCC::HI;
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case ARCCC::NZ:
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return ARCCC::Z;
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case ARCCC::Z:
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return ARCCC::NZ;
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}
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}
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static bool isUncondBranchOpcode(int Opc) { return Opc == ARC::BR; }
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static bool isCondBranchOpcode(int Opc) {
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return Opc == ARC::BRcc_rr_p || Opc == ARC::BRcc_ru6_p;
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}
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static bool isJumpOpcode(int Opc) { return Opc == ARC::J; }
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/// Analyze the branching code at the end of MBB, returning
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/// true if it cannot be understood (e.g. it's a switch dispatch or isn't
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/// implemented for a target). Upon success, this returns false and returns
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/// with the following information in various cases:
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///
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/// 1. If this block ends with no branches (it just falls through to its succ)
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/// just return false, leaving TBB/FBB null.
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/// 2. If this block ends with only an unconditional branch, it sets TBB to be
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/// the destination block.
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/// 3. If this block ends with a conditional branch and it falls through to a
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/// successor block, it sets TBB to be the branch destination block and a
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/// list of operands that evaluate the condition. These operands can be
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/// passed to other TargetInstrInfo methods to create new branches.
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/// 4. If this block ends with a conditional branch followed by an
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/// unconditional branch, it returns the 'true' destination in TBB, the
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/// 'false' destination in FBB, and a list of operands that evaluate the
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/// condition. These operands can be passed to other TargetInstrInfo
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/// methods to create new branches.
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///
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/// Note that RemoveBranch and insertBranch must be implemented to support
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/// cases where this method returns success.
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///
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/// If AllowModify is true, then this routine is allowed to modify the basic
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/// block (e.g. delete instructions after the unconditional branch).
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bool ARCInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const {
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TBB = FBB = nullptr;
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin())
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return false;
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--I;
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while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) {
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// Flag to be raised on unanalyzeable instructions. This is useful in cases
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// where we want to clean up on the end of the basic block before we bail
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// out.
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bool CantAnalyze = false;
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// Skip over DEBUG values and predicated nonterminators.
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while (I->isDebugInstr() || !I->isTerminator()) {
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if (I == MBB.begin())
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return false;
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--I;
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}
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if (isJumpOpcode(I->getOpcode())) {
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// Indirect branches and jump tables can't be analyzed, but we still want
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// to clean up any instructions at the tail of the basic block.
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CantAnalyze = true;
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} else if (isUncondBranchOpcode(I->getOpcode())) {
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TBB = I->getOperand(0).getMBB();
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} else if (isCondBranchOpcode(I->getOpcode())) {
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// Bail out if we encounter multiple conditional branches.
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if (!Cond.empty())
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return true;
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assert(!FBB && "FBB should have been null.");
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FBB = TBB;
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TBB = I->getOperand(0).getMBB();
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Cond.push_back(I->getOperand(1));
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Cond.push_back(I->getOperand(2));
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Cond.push_back(I->getOperand(3));
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} else if (I->isReturn()) {
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// Returns can't be analyzed, but we should run cleanup.
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CantAnalyze = !isPredicated(*I);
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} else {
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// We encountered other unrecognized terminator. Bail out immediately.
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return true;
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}
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// Cleanup code - to be run for unpredicated unconditional branches and
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// returns.
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if (!isPredicated(*I) && (isUncondBranchOpcode(I->getOpcode()) ||
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isJumpOpcode(I->getOpcode()) || I->isReturn())) {
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// Forget any previous condition branch information - it no longer
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// applies.
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Cond.clear();
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FBB = nullptr;
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// If we can modify the function, delete everything below this
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// unconditional branch.
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if (AllowModify) {
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MachineBasicBlock::iterator DI = std::next(I);
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while (DI != MBB.end()) {
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MachineInstr &InstToDelete = *DI;
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++DI;
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InstToDelete.eraseFromParent();
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}
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}
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}
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if (CantAnalyze)
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return true;
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if (I == MBB.begin())
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return false;
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--I;
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}
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// We made it past the terminators without bailing out - we must have
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// analyzed this branch successfully.
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return false;
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}
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unsigned ARCInstrInfo::removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved) const {
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assert(!BytesRemoved && "Code size not handled");
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MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
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if (I == MBB.end())
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return 0;
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if (!isUncondBranchOpcode(I->getOpcode()) &&
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!isCondBranchOpcode(I->getOpcode()))
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return 0;
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// Remove the branch.
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I->eraseFromParent();
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I = MBB.end();
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if (I == MBB.begin())
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return 1;
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--I;
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if (!isCondBranchOpcode(I->getOpcode()))
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return 1;
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// Remove the branch.
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I->eraseFromParent();
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return 2;
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}
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void ARCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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const DebugLoc &dl, MCRegister DestReg,
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MCRegister SrcReg, bool KillSrc) const {
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assert(ARC::GPR32RegClass.contains(SrcReg) &&
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"Only GPR32 src copy supported.");
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assert(ARC::GPR32RegClass.contains(DestReg) &&
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"Only GPR32 dest copy supported.");
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BuildMI(MBB, I, dl, get(ARC::MOV_rr), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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}
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void ARCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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Register SrcReg, bool isKill,
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int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc dl = MBB.findDebugLoc(I);
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = MF.getFrameInfo();
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MachineMemOperand *MMO = MF.getMachineMemOperand(
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MachinePointerInfo::getFixedStack(MF, FrameIndex),
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MachineMemOperand::MOStore, MFI.getObjectSize(FrameIndex),
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MFI.getObjectAlign(FrameIndex));
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assert(MMO && "Couldn't get MachineMemOperand for store to stack.");
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assert(TRI->getSpillSize(*RC) == 4 &&
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"Only support 4-byte stores to stack now.");
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assert(ARC::GPR32RegClass.hasSubClassEq(RC) &&
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"Only support GPR32 stores to stack now.");
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LLVM_DEBUG(dbgs() << "Created store reg=" << printReg(SrcReg, TRI)
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<< " to FrameIndex=" << FrameIndex << "\n");
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BuildMI(MBB, I, dl, get(ARC::ST_rs9))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FrameIndex)
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.addImm(0)
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.addMemOperand(MMO);
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}
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void ARCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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Register DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc dl = MBB.findDebugLoc(I);
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = MF.getFrameInfo();
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MachineMemOperand *MMO = MF.getMachineMemOperand(
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MachinePointerInfo::getFixedStack(MF, FrameIndex),
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MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIndex),
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MFI.getObjectAlign(FrameIndex));
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assert(MMO && "Couldn't get MachineMemOperand for store to stack.");
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assert(TRI->getSpillSize(*RC) == 4 &&
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"Only support 4-byte loads from stack now.");
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assert(ARC::GPR32RegClass.hasSubClassEq(RC) &&
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"Only support GPR32 stores to stack now.");
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LLVM_DEBUG(dbgs() << "Created load reg=" << printReg(DestReg, TRI)
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<< " from FrameIndex=" << FrameIndex << "\n");
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BuildMI(MBB, I, dl, get(ARC::LD_rs9))
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.addReg(DestReg, RegState::Define)
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.addFrameIndex(FrameIndex)
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.addImm(0)
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.addMemOperand(MMO);
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}
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/// Return the inverse opcode of the specified Branch instruction.
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bool ARCInstrInfo::reverseBranchCondition(
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SmallVectorImpl<MachineOperand> &Cond) const {
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assert((Cond.size() == 3) && "Invalid ARC branch condition!");
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Cond[2].setImm(GetOppositeBranchCondition((ARCCC::CondCode)Cond[2].getImm()));
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return false;
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}
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MachineBasicBlock::iterator
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ARCInstrInfo::loadImmediate(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, unsigned Reg,
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uint64_t Value) const {
|
||
|
|
DebugLoc dl = MBB.findDebugLoc(MI);
|
||
|
|
if (isInt<12>(Value)) {
|
||
|
|
return BuildMI(MBB, MI, dl, get(ARC::MOV_rs12), Reg)
|
||
|
|
.addImm(Value)
|
||
|
|
.getInstr();
|
||
|
|
}
|
||
|
|
llvm_unreachable("Need Arc long immediate instructions.");
|
||
|
|
}
|
||
|
|
|
||
|
|
unsigned ARCInstrInfo::insertBranch(MachineBasicBlock &MBB,
|
||
|
|
MachineBasicBlock *TBB,
|
||
|
|
MachineBasicBlock *FBB,
|
||
|
|
ArrayRef<MachineOperand> Cond,
|
||
|
|
const DebugLoc &dl, int *BytesAdded) const {
|
||
|
|
assert(!BytesAdded && "Code size not handled.");
|
||
|
|
|
||
|
|
// Shouldn't be a fall through.
|
||
|
|
assert(TBB && "insertBranch must not be told to insert a fallthrough");
|
||
|
|
assert((Cond.size() == 3 || Cond.size() == 0) &&
|
||
|
|
"ARC branch conditions have two components!");
|
||
|
|
|
||
|
|
if (Cond.empty()) {
|
||
|
|
BuildMI(&MBB, dl, get(ARC::BR)).addMBB(TBB);
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
int BccOpc = Cond[1].isImm() ? ARC::BRcc_ru6_p : ARC::BRcc_rr_p;
|
||
|
|
MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(BccOpc));
|
||
|
|
MIB.addMBB(TBB);
|
||
|
|
for (unsigned i = 0; i < 3; i++) {
|
||
|
|
MIB.add(Cond[i]);
|
||
|
|
}
|
||
|
|
|
||
|
|
// One-way conditional branch.
|
||
|
|
if (!FBB) {
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Two-way conditional branch.
|
||
|
|
BuildMI(&MBB, dl, get(ARC::BR)).addMBB(FBB);
|
||
|
|
return 2;
|
||
|
|
}
|
||
|
|
|
||
|
|
unsigned ARCInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
|
||
|
|
if (MI.isInlineAsm()) {
|
||
|
|
const MachineFunction *MF = MI.getParent()->getParent();
|
||
|
|
const char *AsmStr = MI.getOperand(0).getSymbolName();
|
||
|
|
return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
|
||
|
|
}
|
||
|
|
return MI.getDesc().getSize();
|
||
|
|
}
|
||
|
|
|
||
|
|
bool ARCInstrInfo::isPostIncrement(const MachineInstr &MI) const {
|
||
|
|
const MCInstrDesc &MID = MI.getDesc();
|
||
|
|
const uint64_t F = MID.TSFlags;
|
||
|
|
return ((F >> TSF_AddrModeOff) & TSF_AddModeMask) == PostInc;
|
||
|
|
}
|
||
|
|
|
||
|
|
bool ARCInstrInfo::isPreIncrement(const MachineInstr &MI) const {
|
||
|
|
const MCInstrDesc &MID = MI.getDesc();
|
||
|
|
const uint64_t F = MID.TSFlags;
|
||
|
|
return ((F >> TSF_AddrModeOff) & TSF_AddModeMask) == PreInc;
|
||
|
|
}
|
||
|
|
|
||
|
|
bool ARCInstrInfo::getBaseAndOffsetPosition(const MachineInstr &MI,
|
||
|
|
unsigned &BasePos,
|
||
|
|
unsigned &OffsetPos) const {
|
||
|
|
if (!MI.mayLoad() && !MI.mayStore())
|
||
|
|
return false;
|
||
|
|
|
||
|
|
BasePos = 1;
|
||
|
|
OffsetPos = 2;
|
||
|
|
|
||
|
|
if (isPostIncrement(MI) || isPreIncrement(MI)) {
|
||
|
|
BasePos++;
|
||
|
|
OffsetPos++;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!MI.getOperand(BasePos).isReg() || !MI.getOperand(OffsetPos).isImm())
|
||
|
|
return false;
|
||
|
|
|
||
|
|
return true;
|
||
|
|
}
|