72 lines
2.0 KiB
C++
72 lines
2.0 KiB
C++
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//===-- SIFixVGPRCopies.cpp - Fix VGPR Copies after regalloc --------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// Add implicit use of exec to vector register copies.
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///
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "GCNSubtarget.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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using namespace llvm;
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#define DEBUG_TYPE "si-fix-vgpr-copies"
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namespace {
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class SIFixVGPRCopies : public MachineFunctionPass {
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public:
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static char ID;
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public:
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SIFixVGPRCopies() : MachineFunctionPass(ID) {
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initializeSIFixVGPRCopiesPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override { return "SI Fix VGPR copies"; }
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};
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} // End anonymous namespace.
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INITIALIZE_PASS(SIFixVGPRCopies, DEBUG_TYPE, "SI Fix VGPR copies", false, false)
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char SIFixVGPRCopies::ID = 0;
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char &llvm::SIFixVGPRCopiesID = SIFixVGPRCopies::ID;
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bool SIFixVGPRCopies::runOnMachineFunction(MachineFunction &MF) {
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const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
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const SIRegisterInfo *TRI = ST.getRegisterInfo();
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const SIInstrInfo *TII = ST.getInstrInfo();
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bool Changed = false;
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for (MachineBasicBlock &MBB : MF) {
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for (MachineInstr &MI : MBB) {
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switch (MI.getOpcode()) {
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case AMDGPU::COPY:
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if (TII->isVGPRCopy(MI) && !MI.readsRegister(AMDGPU::EXEC, TRI)) {
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MI.addOperand(MF,
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MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
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LLVM_DEBUG(dbgs() << "Add exec use to " << MI);
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Changed = true;
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}
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break;
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default:
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break;
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}
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}
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}
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return Changed;
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}
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