684 lines
28 KiB
C++
684 lines
28 KiB
C++
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//===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides AMDGPU specific target streamer methods.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUTargetStreamer.h"
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#include "AMDGPUPTNote.h"
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#include "AMDKernelCodeT.h"
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#include "Utils/AMDGPUBaseInfo.h"
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#include "Utils/AMDKernelCodeTUtils.h"
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#include "llvm/BinaryFormat/AMDGPUMetadataVerifier.h"
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#include "llvm/BinaryFormat/ELF.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCELFStreamer.h"
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#include "llvm/MC/MCSectionELF.h"
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#include "llvm/Support/AMDGPUMetadata.h"
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#include "llvm/Support/AMDHSAKernelDescriptor.h"
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#include "llvm/Support/FormattedStream.h"
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using namespace llvm;
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using namespace llvm::AMDGPU;
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//===----------------------------------------------------------------------===//
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// AMDGPUTargetStreamer
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//===----------------------------------------------------------------------===//
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bool AMDGPUTargetStreamer::EmitHSAMetadataV2(StringRef HSAMetadataString) {
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HSAMD::Metadata HSAMetadata;
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if (HSAMD::fromString(HSAMetadataString, HSAMetadata))
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return false;
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return EmitHSAMetadata(HSAMetadata);
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}
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bool AMDGPUTargetStreamer::EmitHSAMetadataV3(StringRef HSAMetadataString) {
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msgpack::Document HSAMetadataDoc;
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if (!HSAMetadataDoc.fromYAML(HSAMetadataString))
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return false;
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return EmitHSAMetadata(HSAMetadataDoc, false);
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}
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StringRef AMDGPUTargetStreamer::getArchNameFromElfMach(unsigned ElfMach) {
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AMDGPU::GPUKind AK;
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switch (ElfMach) {
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default: llvm_unreachable("Unhandled ELF::EF_AMDGPU type");
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case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break;
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case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break;
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case ELF::EF_AMDGPU_MACH_R600_RS880: AK = GK_RS880; break;
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case ELF::EF_AMDGPU_MACH_R600_RV670: AK = GK_RV670; break;
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case ELF::EF_AMDGPU_MACH_R600_RV710: AK = GK_RV710; break;
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case ELF::EF_AMDGPU_MACH_R600_RV730: AK = GK_RV730; break;
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case ELF::EF_AMDGPU_MACH_R600_RV770: AK = GK_RV770; break;
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case ELF::EF_AMDGPU_MACH_R600_CEDAR: AK = GK_CEDAR; break;
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case ELF::EF_AMDGPU_MACH_R600_CYPRESS: AK = GK_CYPRESS; break;
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case ELF::EF_AMDGPU_MACH_R600_JUNIPER: AK = GK_JUNIPER; break;
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case ELF::EF_AMDGPU_MACH_R600_REDWOOD: AK = GK_REDWOOD; break;
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case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break;
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case ELF::EF_AMDGPU_MACH_R600_BARTS: AK = GK_BARTS; break;
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case ELF::EF_AMDGPU_MACH_R600_CAICOS: AK = GK_CAICOS; break;
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case ELF::EF_AMDGPU_MACH_R600_CAYMAN: AK = GK_CAYMAN; break;
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case ELF::EF_AMDGPU_MACH_R600_TURKS: AK = GK_TURKS; break;
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case ELF::EF_AMDGPU_MACH_AMDGCN_GFX600: AK = GK_GFX600; break;
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case ELF::EF_AMDGPU_MACH_AMDGCN_GFX601: AK = GK_GFX601; break;
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case ELF::EF_AMDGPU_MACH_AMDGCN_GFX602: AK = GK_GFX602; break;
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case ELF::EF_AMDGPU_MACH_AMDGCN_GFX700: AK = GK_GFX700; break;
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case ELF::EF_AMDGPU_MACH_AMDGCN_GFX701: AK = GK_GFX701; break;
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case ELF::EF_AMDGPU_MACH_AMDGCN_GFX702: AK = GK_GFX702; break;
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case ELF::EF_AMDGPU_MACH_AMDGCN_GFX703: AK = GK_GFX703; break;
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case ELF::EF_AMDGPU_MACH_AMDGCN_GFX704: AK = GK_GFX704; break;
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case ELF::EF_AMDGPU_MACH_AMDGCN_GFX705: AK = GK_GFX705; break;
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case ELF::EF_AMDGPU_MACH_AMDGCN_GFX801: AK = GK_GFX801; break;
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case ELF::EF_AMDGPU_MACH_AMDGCN_GFX802: AK = GK_GFX802; break;
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case ELF::EF_AMDGPU_MACH_AMDGCN_GFX803: AK = GK_GFX803; break;
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case ELF::EF_AMDGPU_MACH_AMDGCN_GFX805: AK = GK_GFX805; break;
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case ELF::EF_AMDGPU_MACH_AMDGCN_GFX810: AK = GK_GFX810; break;
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case ELF::EF_AMDGPU_MACH_AMDGCN_GFX900: AK = GK_GFX900; break;
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case ELF::EF_AMDGPU_MACH_AMDGCN_GFX902: AK = GK_GFX902; break;
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case ELF::EF_AMDGPU_MACH_AMDGCN_GFX904: AK = GK_GFX904; break;
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case ELF::EF_AMDGPU_MACH_AMDGCN_GFX906: AK = GK_GFX906; break;
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case ELF::EF_AMDGPU_MACH_AMDGCN_GFX908: AK = GK_GFX908; break;
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case ELF::EF_AMDGPU_MACH_AMDGCN_GFX909: AK = GK_GFX909; break;
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case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C: AK = GK_GFX90C; break;
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case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010: AK = GK_GFX1010; break;
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case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011: AK = GK_GFX1011; break;
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case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012: AK = GK_GFX1012; break;
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case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030: AK = GK_GFX1030; break;
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case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031: AK = GK_GFX1031; break;
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case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032: AK = GK_GFX1032; break;
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case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033: AK = GK_GFX1033; break;
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case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break;
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}
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StringRef GPUName = getArchNameAMDGCN(AK);
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if (GPUName != "")
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return GPUName;
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return getArchNameR600(AK);
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}
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unsigned AMDGPUTargetStreamer::getElfMach(StringRef GPU) {
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AMDGPU::GPUKind AK = parseArchAMDGCN(GPU);
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if (AK == AMDGPU::GPUKind::GK_NONE)
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AK = parseArchR600(GPU);
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switch (AK) {
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case GK_R600: return ELF::EF_AMDGPU_MACH_R600_R600;
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case GK_R630: return ELF::EF_AMDGPU_MACH_R600_R630;
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case GK_RS880: return ELF::EF_AMDGPU_MACH_R600_RS880;
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case GK_RV670: return ELF::EF_AMDGPU_MACH_R600_RV670;
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case GK_RV710: return ELF::EF_AMDGPU_MACH_R600_RV710;
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case GK_RV730: return ELF::EF_AMDGPU_MACH_R600_RV730;
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case GK_RV770: return ELF::EF_AMDGPU_MACH_R600_RV770;
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case GK_CEDAR: return ELF::EF_AMDGPU_MACH_R600_CEDAR;
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case GK_CYPRESS: return ELF::EF_AMDGPU_MACH_R600_CYPRESS;
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case GK_JUNIPER: return ELF::EF_AMDGPU_MACH_R600_JUNIPER;
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case GK_REDWOOD: return ELF::EF_AMDGPU_MACH_R600_REDWOOD;
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case GK_SUMO: return ELF::EF_AMDGPU_MACH_R600_SUMO;
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case GK_BARTS: return ELF::EF_AMDGPU_MACH_R600_BARTS;
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case GK_CAICOS: return ELF::EF_AMDGPU_MACH_R600_CAICOS;
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case GK_CAYMAN: return ELF::EF_AMDGPU_MACH_R600_CAYMAN;
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case GK_TURKS: return ELF::EF_AMDGPU_MACH_R600_TURKS;
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case GK_GFX600: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX600;
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case GK_GFX601: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX601;
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case GK_GFX602: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX602;
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case GK_GFX700: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX700;
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case GK_GFX701: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX701;
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case GK_GFX702: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX702;
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case GK_GFX703: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX703;
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case GK_GFX704: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX704;
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case GK_GFX705: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX705;
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case GK_GFX801: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX801;
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case GK_GFX802: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX802;
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case GK_GFX803: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX803;
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case GK_GFX805: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX805;
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case GK_GFX810: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX810;
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case GK_GFX900: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX900;
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case GK_GFX902: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX902;
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case GK_GFX904: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX904;
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case GK_GFX906: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX906;
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case GK_GFX908: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX908;
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case GK_GFX909: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX909;
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case GK_GFX90C: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C;
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case GK_GFX1010: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010;
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case GK_GFX1011: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011;
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case GK_GFX1012: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012;
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case GK_GFX1030: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030;
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case GK_GFX1031: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031;
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case GK_GFX1032: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032;
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case GK_GFX1033: return ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033;
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case GK_NONE: return ELF::EF_AMDGPU_MACH_NONE;
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}
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llvm_unreachable("unknown GPU");
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}
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//===----------------------------------------------------------------------===//
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// AMDGPUTargetAsmStreamer
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//===----------------------------------------------------------------------===//
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AMDGPUTargetAsmStreamer::AMDGPUTargetAsmStreamer(MCStreamer &S,
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formatted_raw_ostream &OS)
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: AMDGPUTargetStreamer(S), OS(OS) { }
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// A hook for emitting stuff at the end.
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// We use it for emitting the accumulated PAL metadata as directives.
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// The PAL metadata is reset after it is emitted.
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void AMDGPUTargetAsmStreamer::finish() {
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std::string S;
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getPALMetadata()->toString(S);
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OS << S;
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// Reset the pal metadata so its data will not affect a compilation that
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// reuses this object.
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getPALMetadata()->reset();
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}
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void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget(StringRef Target) {
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OS << "\t.amdgcn_target \"" << Target << "\"\n";
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}
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void AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectVersion(
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uint32_t Major, uint32_t Minor) {
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OS << "\t.hsa_code_object_version " <<
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Twine(Major) << "," << Twine(Minor) << '\n';
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}
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void
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AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectISA(uint32_t Major,
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uint32_t Minor,
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uint32_t Stepping,
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StringRef VendorName,
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StringRef ArchName) {
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OS << "\t.hsa_code_object_isa " <<
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Twine(Major) << "," << Twine(Minor) << "," << Twine(Stepping) <<
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",\"" << VendorName << "\",\"" << ArchName << "\"\n";
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}
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void
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AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) {
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OS << "\t.amd_kernel_code_t\n";
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dumpAmdKernelCode(&Header, OS, "\t\t");
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OS << "\t.end_amd_kernel_code_t\n";
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}
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void AMDGPUTargetAsmStreamer::EmitAMDGPUSymbolType(StringRef SymbolName,
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unsigned Type) {
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switch (Type) {
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default: llvm_unreachable("Invalid AMDGPU symbol type");
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case ELF::STT_AMDGPU_HSA_KERNEL:
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OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ;
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break;
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}
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}
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void AMDGPUTargetAsmStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size,
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Align Alignment) {
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OS << "\t.amdgpu_lds " << Symbol->getName() << ", " << Size << ", "
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<< Alignment.value() << '\n';
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}
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bool AMDGPUTargetAsmStreamer::EmitISAVersion(StringRef IsaVersionString) {
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OS << "\t.amd_amdgpu_isa \"" << IsaVersionString << "\"\n";
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return true;
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}
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bool AMDGPUTargetAsmStreamer::EmitHSAMetadata(
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const AMDGPU::HSAMD::Metadata &HSAMetadata) {
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std::string HSAMetadataString;
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if (HSAMD::toString(HSAMetadata, HSAMetadataString))
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return false;
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OS << '\t' << HSAMD::AssemblerDirectiveBegin << '\n';
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OS << HSAMetadataString << '\n';
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OS << '\t' << HSAMD::AssemblerDirectiveEnd << '\n';
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return true;
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}
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bool AMDGPUTargetAsmStreamer::EmitHSAMetadata(
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msgpack::Document &HSAMetadataDoc, bool Strict) {
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HSAMD::V3::MetadataVerifier Verifier(Strict);
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if (!Verifier.verify(HSAMetadataDoc.getRoot()))
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return false;
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std::string HSAMetadataString;
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raw_string_ostream StrOS(HSAMetadataString);
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HSAMetadataDoc.toYAML(StrOS);
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OS << '\t' << HSAMD::V3::AssemblerDirectiveBegin << '\n';
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OS << StrOS.str() << '\n';
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OS << '\t' << HSAMD::V3::AssemblerDirectiveEnd << '\n';
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return true;
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}
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bool AMDGPUTargetAsmStreamer::EmitCodeEnd() {
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const uint32_t Encoded_s_code_end = 0xbf9f0000;
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OS << "\t.p2alignl 6, " << Encoded_s_code_end << '\n';
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OS << "\t.fill 48, 4, " << Encoded_s_code_end << '\n';
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return true;
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}
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void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(
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const MCSubtargetInfo &STI, StringRef KernelName,
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const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR,
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bool ReserveVCC, bool ReserveFlatScr, bool ReserveXNACK) {
|
||
|
|
IsaVersion IVersion = getIsaVersion(STI.getCPU());
|
||
|
|
|
||
|
|
OS << "\t.amdhsa_kernel " << KernelName << '\n';
|
||
|
|
|
||
|
|
#define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \
|
||
|
|
STREAM << "\t\t" << DIRECTIVE << " " \
|
||
|
|
<< AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n';
|
||
|
|
|
||
|
|
OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size
|
||
|
|
<< '\n';
|
||
|
|
OS << "\t\t.amdhsa_private_segment_fixed_size "
|
||
|
|
<< KD.private_segment_fixed_size << '\n';
|
||
|
|
|
||
|
|
PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_buffer", KD,
|
||
|
|
kernel_code_properties,
|
||
|
|
amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER);
|
||
|
|
PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD,
|
||
|
|
kernel_code_properties,
|
||
|
|
amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR);
|
||
|
|
PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD,
|
||
|
|
kernel_code_properties,
|
||
|
|
amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR);
|
||
|
|
PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD,
|
||
|
|
kernel_code_properties,
|
||
|
|
amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR);
|
||
|
|
PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD,
|
||
|
|
kernel_code_properties,
|
||
|
|
amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID);
|
||
|
|
PRINT_FIELD(OS, ".amdhsa_user_sgpr_flat_scratch_init", KD,
|
||
|
|
kernel_code_properties,
|
||
|
|
amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT);
|
||
|
|
PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_size", KD,
|
||
|
|
kernel_code_properties,
|
||
|
|
amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE);
|
||
|
|
if (IVersion.Major >= 10)
|
||
|
|
PRINT_FIELD(OS, ".amdhsa_wavefront_size32", KD,
|
||
|
|
kernel_code_properties,
|
||
|
|
amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32);
|
||
|
|
PRINT_FIELD(
|
||
|
|
OS, ".amdhsa_system_sgpr_private_segment_wavefront_offset", KD,
|
||
|
|
compute_pgm_rsrc2,
|
||
|
|
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT);
|
||
|
|
PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD,
|
||
|
|
compute_pgm_rsrc2,
|
||
|
|
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X);
|
||
|
|
PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD,
|
||
|
|
compute_pgm_rsrc2,
|
||
|
|
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y);
|
||
|
|
PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD,
|
||
|
|
compute_pgm_rsrc2,
|
||
|
|
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z);
|
||
|
|
PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD,
|
||
|
|
compute_pgm_rsrc2,
|
||
|
|
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO);
|
||
|
|
PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD,
|
||
|
|
compute_pgm_rsrc2,
|
||
|
|
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID);
|
||
|
|
|
||
|
|
// These directives are required.
|
||
|
|
OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n';
|
||
|
|
OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n';
|
||
|
|
|
||
|
|
if (!ReserveVCC)
|
||
|
|
OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n';
|
||
|
|
if (IVersion.Major >= 7 && !ReserveFlatScr)
|
||
|
|
OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n';
|
||
|
|
if (IVersion.Major >= 8 && ReserveXNACK != hasXNACK(STI))
|
||
|
|
OS << "\t\t.amdhsa_reserve_xnack_mask " << ReserveXNACK << '\n';
|
||
|
|
|
||
|
|
PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD,
|
||
|
|
compute_pgm_rsrc1,
|
||
|
|
amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32);
|
||
|
|
PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD,
|
||
|
|
compute_pgm_rsrc1,
|
||
|
|
amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64);
|
||
|
|
PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD,
|
||
|
|
compute_pgm_rsrc1,
|
||
|
|
amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32);
|
||
|
|
PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD,
|
||
|
|
compute_pgm_rsrc1,
|
||
|
|
amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64);
|
||
|
|
PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD,
|
||
|
|
compute_pgm_rsrc1,
|
||
|
|
amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP);
|
||
|
|
PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD,
|
||
|
|
compute_pgm_rsrc1,
|
||
|
|
amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE);
|
||
|
|
if (IVersion.Major >= 9)
|
||
|
|
PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD,
|
||
|
|
compute_pgm_rsrc1,
|
||
|
|
amdhsa::COMPUTE_PGM_RSRC1_FP16_OVFL);
|
||
|
|
if (IVersion.Major >= 10) {
|
||
|
|
PRINT_FIELD(OS, ".amdhsa_workgroup_processor_mode", KD,
|
||
|
|
compute_pgm_rsrc1,
|
||
|
|
amdhsa::COMPUTE_PGM_RSRC1_WGP_MODE);
|
||
|
|
PRINT_FIELD(OS, ".amdhsa_memory_ordered", KD,
|
||
|
|
compute_pgm_rsrc1,
|
||
|
|
amdhsa::COMPUTE_PGM_RSRC1_MEM_ORDERED);
|
||
|
|
PRINT_FIELD(OS, ".amdhsa_forward_progress", KD,
|
||
|
|
compute_pgm_rsrc1,
|
||
|
|
amdhsa::COMPUTE_PGM_RSRC1_FWD_PROGRESS);
|
||
|
|
}
|
||
|
|
PRINT_FIELD(
|
||
|
|
OS, ".amdhsa_exception_fp_ieee_invalid_op", KD,
|
||
|
|
compute_pgm_rsrc2,
|
||
|
|
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION);
|
||
|
|
PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD,
|
||
|
|
compute_pgm_rsrc2,
|
||
|
|
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE);
|
||
|
|
PRINT_FIELD(
|
||
|
|
OS, ".amdhsa_exception_fp_ieee_div_zero", KD,
|
||
|
|
compute_pgm_rsrc2,
|
||
|
|
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO);
|
||
|
|
PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD,
|
||
|
|
compute_pgm_rsrc2,
|
||
|
|
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW);
|
||
|
|
PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD,
|
||
|
|
compute_pgm_rsrc2,
|
||
|
|
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW);
|
||
|
|
PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD,
|
||
|
|
compute_pgm_rsrc2,
|
||
|
|
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT);
|
||
|
|
PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD,
|
||
|
|
compute_pgm_rsrc2,
|
||
|
|
amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO);
|
||
|
|
#undef PRINT_FIELD
|
||
|
|
|
||
|
|
OS << "\t.end_amdhsa_kernel\n";
|
||
|
|
}
|
||
|
|
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
// AMDGPUTargetELFStreamer
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
|
||
|
|
AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer(MCStreamer &S,
|
||
|
|
const MCSubtargetInfo &STI)
|
||
|
|
: AMDGPUTargetStreamer(S), Streamer(S), Os(STI.getTargetTriple().getOS()) {
|
||
|
|
MCAssembler &MCA = getStreamer().getAssembler();
|
||
|
|
unsigned EFlags = MCA.getELFHeaderEFlags();
|
||
|
|
|
||
|
|
EFlags &= ~ELF::EF_AMDGPU_MACH;
|
||
|
|
EFlags |= getElfMach(STI.getCPU());
|
||
|
|
|
||
|
|
EFlags &= ~ELF::EF_AMDGPU_XNACK;
|
||
|
|
if (AMDGPU::hasXNACK(STI))
|
||
|
|
EFlags |= ELF::EF_AMDGPU_XNACK;
|
||
|
|
|
||
|
|
EFlags &= ~ELF::EF_AMDGPU_SRAM_ECC;
|
||
|
|
if (AMDGPU::hasSRAMECC(STI))
|
||
|
|
EFlags |= ELF::EF_AMDGPU_SRAM_ECC;
|
||
|
|
|
||
|
|
MCA.setELFHeaderEFlags(EFlags);
|
||
|
|
}
|
||
|
|
|
||
|
|
MCELFStreamer &AMDGPUTargetELFStreamer::getStreamer() {
|
||
|
|
return static_cast<MCELFStreamer &>(Streamer);
|
||
|
|
}
|
||
|
|
|
||
|
|
// A hook for emitting stuff at the end.
|
||
|
|
// We use it for emitting the accumulated PAL metadata as a .note record.
|
||
|
|
// The PAL metadata is reset after it is emitted.
|
||
|
|
void AMDGPUTargetELFStreamer::finish() {
|
||
|
|
std::string Blob;
|
||
|
|
const char *Vendor = getPALMetadata()->getVendor();
|
||
|
|
unsigned Type = getPALMetadata()->getType();
|
||
|
|
getPALMetadata()->toBlob(Type, Blob);
|
||
|
|
if (Blob.empty())
|
||
|
|
return;
|
||
|
|
EmitNote(Vendor, MCConstantExpr::create(Blob.size(), getContext()), Type,
|
||
|
|
[&](MCELFStreamer &OS) { OS.emitBytes(Blob); });
|
||
|
|
|
||
|
|
// Reset the pal metadata so its data will not affect a compilation that
|
||
|
|
// reuses this object.
|
||
|
|
getPALMetadata()->reset();
|
||
|
|
}
|
||
|
|
|
||
|
|
void AMDGPUTargetELFStreamer::EmitNote(
|
||
|
|
StringRef Name, const MCExpr *DescSZ, unsigned NoteType,
|
||
|
|
function_ref<void(MCELFStreamer &)> EmitDesc) {
|
||
|
|
auto &S = getStreamer();
|
||
|
|
auto &Context = S.getContext();
|
||
|
|
|
||
|
|
auto NameSZ = Name.size() + 1;
|
||
|
|
|
||
|
|
unsigned NoteFlags = 0;
|
||
|
|
// TODO Apparently, this is currently needed for OpenCL as mentioned in
|
||
|
|
// https://reviews.llvm.org/D74995
|
||
|
|
if (Os == Triple::AMDHSA)
|
||
|
|
NoteFlags = ELF::SHF_ALLOC;
|
||
|
|
|
||
|
|
S.PushSection();
|
||
|
|
S.SwitchSection(
|
||
|
|
Context.getELFSection(ElfNote::SectionName, ELF::SHT_NOTE, NoteFlags));
|
||
|
|
S.emitInt32(NameSZ); // namesz
|
||
|
|
S.emitValue(DescSZ, 4); // descz
|
||
|
|
S.emitInt32(NoteType); // type
|
||
|
|
S.emitBytes(Name); // name
|
||
|
|
S.emitValueToAlignment(4, 0, 1, 0); // padding 0
|
||
|
|
EmitDesc(S); // desc
|
||
|
|
S.emitValueToAlignment(4, 0, 1, 0); // padding 0
|
||
|
|
S.PopSection();
|
||
|
|
}
|
||
|
|
|
||
|
|
void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget(StringRef Target) {}
|
||
|
|
|
||
|
|
void AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectVersion(
|
||
|
|
uint32_t Major, uint32_t Minor) {
|
||
|
|
|
||
|
|
EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(8, getContext()),
|
||
|
|
ElfNote::NT_AMDGPU_HSA_CODE_OBJECT_VERSION, [&](MCELFStreamer &OS) {
|
||
|
|
OS.emitInt32(Major);
|
||
|
|
OS.emitInt32(Minor);
|
||
|
|
});
|
||
|
|
}
|
||
|
|
|
||
|
|
void
|
||
|
|
AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectISA(uint32_t Major,
|
||
|
|
uint32_t Minor,
|
||
|
|
uint32_t Stepping,
|
||
|
|
StringRef VendorName,
|
||
|
|
StringRef ArchName) {
|
||
|
|
uint16_t VendorNameSize = VendorName.size() + 1;
|
||
|
|
uint16_t ArchNameSize = ArchName.size() + 1;
|
||
|
|
|
||
|
|
unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) +
|
||
|
|
sizeof(Major) + sizeof(Minor) + sizeof(Stepping) +
|
||
|
|
VendorNameSize + ArchNameSize;
|
||
|
|
|
||
|
|
EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(DescSZ, getContext()),
|
||
|
|
ElfNote::NT_AMDGPU_HSA_ISA, [&](MCELFStreamer &OS) {
|
||
|
|
OS.emitInt16(VendorNameSize);
|
||
|
|
OS.emitInt16(ArchNameSize);
|
||
|
|
OS.emitInt32(Major);
|
||
|
|
OS.emitInt32(Minor);
|
||
|
|
OS.emitInt32(Stepping);
|
||
|
|
OS.emitBytes(VendorName);
|
||
|
|
OS.emitInt8(0); // NULL terminate VendorName
|
||
|
|
OS.emitBytes(ArchName);
|
||
|
|
OS.emitInt8(0); // NULL terminte ArchName
|
||
|
|
});
|
||
|
|
}
|
||
|
|
|
||
|
|
void
|
||
|
|
AMDGPUTargetELFStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) {
|
||
|
|
|
||
|
|
MCStreamer &OS = getStreamer();
|
||
|
|
OS.PushSection();
|
||
|
|
OS.emitBytes(StringRef((const char*)&Header, sizeof(Header)));
|
||
|
|
OS.PopSection();
|
||
|
|
}
|
||
|
|
|
||
|
|
void AMDGPUTargetELFStreamer::EmitAMDGPUSymbolType(StringRef SymbolName,
|
||
|
|
unsigned Type) {
|
||
|
|
MCSymbolELF *Symbol = cast<MCSymbolELF>(
|
||
|
|
getStreamer().getContext().getOrCreateSymbol(SymbolName));
|
||
|
|
Symbol->setType(Type);
|
||
|
|
}
|
||
|
|
|
||
|
|
void AMDGPUTargetELFStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size,
|
||
|
|
Align Alignment) {
|
||
|
|
MCSymbolELF *SymbolELF = cast<MCSymbolELF>(Symbol);
|
||
|
|
SymbolELF->setType(ELF::STT_OBJECT);
|
||
|
|
|
||
|
|
if (!SymbolELF->isBindingSet()) {
|
||
|
|
SymbolELF->setBinding(ELF::STB_GLOBAL);
|
||
|
|
SymbolELF->setExternal(true);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (SymbolELF->declareCommon(Size, Alignment.value(), true)) {
|
||
|
|
report_fatal_error("Symbol: " + Symbol->getName() +
|
||
|
|
" redeclared as different type");
|
||
|
|
}
|
||
|
|
|
||
|
|
SymbolELF->setIndex(ELF::SHN_AMDGPU_LDS);
|
||
|
|
SymbolELF->setSize(MCConstantExpr::create(Size, getContext()));
|
||
|
|
}
|
||
|
|
|
||
|
|
bool AMDGPUTargetELFStreamer::EmitISAVersion(StringRef IsaVersionString) {
|
||
|
|
// Create two labels to mark the beginning and end of the desc field
|
||
|
|
// and a MCExpr to calculate the size of the desc field.
|
||
|
|
auto &Context = getContext();
|
||
|
|
auto *DescBegin = Context.createTempSymbol();
|
||
|
|
auto *DescEnd = Context.createTempSymbol();
|
||
|
|
auto *DescSZ = MCBinaryExpr::createSub(
|
||
|
|
MCSymbolRefExpr::create(DescEnd, Context),
|
||
|
|
MCSymbolRefExpr::create(DescBegin, Context), Context);
|
||
|
|
|
||
|
|
EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_AMDGPU_ISA,
|
||
|
|
[&](MCELFStreamer &OS) {
|
||
|
|
OS.emitLabel(DescBegin);
|
||
|
|
OS.emitBytes(IsaVersionString);
|
||
|
|
OS.emitLabel(DescEnd);
|
||
|
|
});
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
bool AMDGPUTargetELFStreamer::EmitHSAMetadata(msgpack::Document &HSAMetadataDoc,
|
||
|
|
bool Strict) {
|
||
|
|
HSAMD::V3::MetadataVerifier Verifier(Strict);
|
||
|
|
if (!Verifier.verify(HSAMetadataDoc.getRoot()))
|
||
|
|
return false;
|
||
|
|
|
||
|
|
std::string HSAMetadataString;
|
||
|
|
HSAMetadataDoc.writeToBlob(HSAMetadataString);
|
||
|
|
|
||
|
|
// Create two labels to mark the beginning and end of the desc field
|
||
|
|
// and a MCExpr to calculate the size of the desc field.
|
||
|
|
auto &Context = getContext();
|
||
|
|
auto *DescBegin = Context.createTempSymbol();
|
||
|
|
auto *DescEnd = Context.createTempSymbol();
|
||
|
|
auto *DescSZ = MCBinaryExpr::createSub(
|
||
|
|
MCSymbolRefExpr::create(DescEnd, Context),
|
||
|
|
MCSymbolRefExpr::create(DescBegin, Context), Context);
|
||
|
|
|
||
|
|
EmitNote(ElfNote::NoteNameV3, DescSZ, ELF::NT_AMDGPU_METADATA,
|
||
|
|
[&](MCELFStreamer &OS) {
|
||
|
|
OS.emitLabel(DescBegin);
|
||
|
|
OS.emitBytes(HSAMetadataString);
|
||
|
|
OS.emitLabel(DescEnd);
|
||
|
|
});
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
bool AMDGPUTargetELFStreamer::EmitHSAMetadata(
|
||
|
|
const AMDGPU::HSAMD::Metadata &HSAMetadata) {
|
||
|
|
std::string HSAMetadataString;
|
||
|
|
if (HSAMD::toString(HSAMetadata, HSAMetadataString))
|
||
|
|
return false;
|
||
|
|
|
||
|
|
// Create two labels to mark the beginning and end of the desc field
|
||
|
|
// and a MCExpr to calculate the size of the desc field.
|
||
|
|
auto &Context = getContext();
|
||
|
|
auto *DescBegin = Context.createTempSymbol();
|
||
|
|
auto *DescEnd = Context.createTempSymbol();
|
||
|
|
auto *DescSZ = MCBinaryExpr::createSub(
|
||
|
|
MCSymbolRefExpr::create(DescEnd, Context),
|
||
|
|
MCSymbolRefExpr::create(DescBegin, Context), Context);
|
||
|
|
|
||
|
|
EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_AMDGPU_HSA_METADATA,
|
||
|
|
[&](MCELFStreamer &OS) {
|
||
|
|
OS.emitLabel(DescBegin);
|
||
|
|
OS.emitBytes(HSAMetadataString);
|
||
|
|
OS.emitLabel(DescEnd);
|
||
|
|
});
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
bool AMDGPUTargetELFStreamer::EmitCodeEnd() {
|
||
|
|
const uint32_t Encoded_s_code_end = 0xbf9f0000;
|
||
|
|
|
||
|
|
MCStreamer &OS = getStreamer();
|
||
|
|
OS.PushSection();
|
||
|
|
OS.emitValueToAlignment(64, Encoded_s_code_end, 4);
|
||
|
|
for (unsigned I = 0; I < 48; ++I)
|
||
|
|
OS.emitInt32(Encoded_s_code_end);
|
||
|
|
OS.PopSection();
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor(
|
||
|
|
const MCSubtargetInfo &STI, StringRef KernelName,
|
||
|
|
const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR,
|
||
|
|
uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr,
|
||
|
|
bool ReserveXNACK) {
|
||
|
|
auto &Streamer = getStreamer();
|
||
|
|
auto &Context = Streamer.getContext();
|
||
|
|
|
||
|
|
MCSymbolELF *KernelCodeSymbol = cast<MCSymbolELF>(
|
||
|
|
Context.getOrCreateSymbol(Twine(KernelName)));
|
||
|
|
MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>(
|
||
|
|
Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd")));
|
||
|
|
|
||
|
|
// Copy kernel descriptor symbol's binding, other and visibility from the
|
||
|
|
// kernel code symbol.
|
||
|
|
KernelDescriptorSymbol->setBinding(KernelCodeSymbol->getBinding());
|
||
|
|
KernelDescriptorSymbol->setOther(KernelCodeSymbol->getOther());
|
||
|
|
KernelDescriptorSymbol->setVisibility(KernelCodeSymbol->getVisibility());
|
||
|
|
// Kernel descriptor symbol's type and size are fixed.
|
||
|
|
KernelDescriptorSymbol->setType(ELF::STT_OBJECT);
|
||
|
|
KernelDescriptorSymbol->setSize(
|
||
|
|
MCConstantExpr::create(sizeof(KernelDescriptor), Context));
|
||
|
|
|
||
|
|
// The visibility of the kernel code symbol must be protected or less to allow
|
||
|
|
// static relocations from the kernel descriptor to be used.
|
||
|
|
if (KernelCodeSymbol->getVisibility() == ELF::STV_DEFAULT)
|
||
|
|
KernelCodeSymbol->setVisibility(ELF::STV_PROTECTED);
|
||
|
|
|
||
|
|
Streamer.emitLabel(KernelDescriptorSymbol);
|
||
|
|
Streamer.emitInt32(KernelDescriptor.group_segment_fixed_size);
|
||
|
|
Streamer.emitInt32(KernelDescriptor.private_segment_fixed_size);
|
||
|
|
for (uint8_t Res : KernelDescriptor.reserved0)
|
||
|
|
Streamer.emitInt8(Res);
|
||
|
|
// FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The
|
||
|
|
// expression being created is:
|
||
|
|
// (start of kernel code) - (start of kernel descriptor)
|
||
|
|
// It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64.
|
||
|
|
Streamer.emitValue(MCBinaryExpr::createSub(
|
||
|
|
MCSymbolRefExpr::create(
|
||
|
|
KernelCodeSymbol, MCSymbolRefExpr::VK_AMDGPU_REL64, Context),
|
||
|
|
MCSymbolRefExpr::create(
|
||
|
|
KernelDescriptorSymbol, MCSymbolRefExpr::VK_None, Context),
|
||
|
|
Context),
|
||
|
|
sizeof(KernelDescriptor.kernel_code_entry_byte_offset));
|
||
|
|
for (uint8_t Res : KernelDescriptor.reserved1)
|
||
|
|
Streamer.emitInt8(Res);
|
||
|
|
Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc3);
|
||
|
|
Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc1);
|
||
|
|
Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc2);
|
||
|
|
Streamer.emitInt16(KernelDescriptor.kernel_code_properties);
|
||
|
|
for (uint8_t Res : KernelDescriptor.reserved2)
|
||
|
|
Streamer.emitInt8(Res);
|
||
|
|
}
|