595 lines
20 KiB
C++
595 lines
20 KiB
C++
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//=======- GCNDPPCombine.cpp - optimization for DPP instructions ---==========//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// The pass combines V_MOV_B32_dpp instruction with its VALU uses as a DPP src0
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// operand. If any of the use instruction cannot be combined with the mov the
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// whole sequence is reverted.
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//
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// $old = ...
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// $dpp_value = V_MOV_B32_dpp $old, $vgpr_to_be_read_from_other_lane,
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// dpp_controls..., $row_mask, $bank_mask, $bound_ctrl
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// $res = VALU $dpp_value [, src1]
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//
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// to
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//
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// $res = VALU_DPP $combined_old, $vgpr_to_be_read_from_other_lane, [src1,]
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// dpp_controls..., $row_mask, $bank_mask, $combined_bound_ctrl
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//
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// Combining rules :
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//
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// if $row_mask and $bank_mask are fully enabled (0xF) and
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// $bound_ctrl==DPP_BOUND_ZERO or $old==0
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// -> $combined_old = undef,
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// $combined_bound_ctrl = DPP_BOUND_ZERO
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//
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// if the VALU op is binary and
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// $bound_ctrl==DPP_BOUND_OFF and
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// $old==identity value (immediate) for the VALU op
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// -> $combined_old = src1,
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// $combined_bound_ctrl = DPP_BOUND_OFF
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//
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// Otherwise cancel.
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//
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// The mov_dpp instruction should reside in the same BB as all its uses
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "GCNSubtarget.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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using namespace llvm;
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#define DEBUG_TYPE "gcn-dpp-combine"
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STATISTIC(NumDPPMovsCombined, "Number of DPP moves combined.");
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namespace {
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class GCNDPPCombine : public MachineFunctionPass {
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MachineRegisterInfo *MRI;
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const SIInstrInfo *TII;
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using RegSubRegPair = TargetInstrInfo::RegSubRegPair;
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MachineOperand *getOldOpndValue(MachineOperand &OldOpnd) const;
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MachineInstr *createDPPInst(MachineInstr &OrigMI,
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MachineInstr &MovMI,
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RegSubRegPair CombOldVGPR,
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MachineOperand *OldOpnd,
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bool CombBCZ) const;
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MachineInstr *createDPPInst(MachineInstr &OrigMI,
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MachineInstr &MovMI,
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RegSubRegPair CombOldVGPR,
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bool CombBCZ) const;
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bool hasNoImmOrEqual(MachineInstr &MI,
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unsigned OpndName,
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int64_t Value,
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int64_t Mask = -1) const;
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bool combineDPPMov(MachineInstr &MI) const;
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public:
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static char ID;
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GCNDPPCombine() : MachineFunctionPass(ID) {
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initializeGCNDPPCombinePass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override { return "GCN DPP Combine"; }
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties()
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.set(MachineFunctionProperties::Property::IsSSA);
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}
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private:
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int getDPPOp(unsigned Op) const;
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};
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} // end anonymous namespace
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INITIALIZE_PASS(GCNDPPCombine, DEBUG_TYPE, "GCN DPP Combine", false, false)
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char GCNDPPCombine::ID = 0;
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char &llvm::GCNDPPCombineID = GCNDPPCombine::ID;
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FunctionPass *llvm::createGCNDPPCombinePass() {
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return new GCNDPPCombine();
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}
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int GCNDPPCombine::getDPPOp(unsigned Op) const {
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auto DPP32 = AMDGPU::getDPPOp32(Op);
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if (DPP32 == -1) {
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auto E32 = AMDGPU::getVOPe32(Op);
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DPP32 = (E32 == -1)? -1 : AMDGPU::getDPPOp32(E32);
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}
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return (DPP32 == -1 || TII->pseudoToMCOpcode(DPP32) == -1) ? -1 : DPP32;
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}
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// tracks the register operand definition and returns:
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// 1. immediate operand used to initialize the register if found
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// 2. nullptr if the register operand is undef
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// 3. the operand itself otherwise
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MachineOperand *GCNDPPCombine::getOldOpndValue(MachineOperand &OldOpnd) const {
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auto *Def = getVRegSubRegDef(getRegSubRegPair(OldOpnd), *MRI);
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if (!Def)
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return nullptr;
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switch(Def->getOpcode()) {
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default: break;
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case AMDGPU::IMPLICIT_DEF:
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return nullptr;
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case AMDGPU::COPY:
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case AMDGPU::V_MOV_B32_e32: {
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auto &Op1 = Def->getOperand(1);
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if (Op1.isImm())
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return &Op1;
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break;
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}
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}
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return &OldOpnd;
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}
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MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI,
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MachineInstr &MovMI,
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RegSubRegPair CombOldVGPR,
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bool CombBCZ) const {
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assert(MovMI.getOpcode() == AMDGPU::V_MOV_B32_dpp);
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auto OrigOp = OrigMI.getOpcode();
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auto DPPOp = getDPPOp(OrigOp);
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if (DPPOp == -1) {
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LLVM_DEBUG(dbgs() << " failed: no DPP opcode\n");
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return nullptr;
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}
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auto DPPInst = BuildMI(*OrigMI.getParent(), OrigMI,
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OrigMI.getDebugLoc(), TII->get(DPPOp))
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.setMIFlags(OrigMI.getFlags());
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bool Fail = false;
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do {
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auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst);
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assert(Dst);
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DPPInst.add(*Dst);
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int NumOperands = 1;
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const int OldIdx = AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::old);
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if (OldIdx != -1) {
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assert(OldIdx == NumOperands);
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assert(isOfRegClass(CombOldVGPR, AMDGPU::VGPR_32RegClass, *MRI));
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auto *Def = getVRegSubRegDef(CombOldVGPR, *MRI);
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DPPInst.addReg(CombOldVGPR.Reg, Def ? 0 : RegState::Undef,
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CombOldVGPR.SubReg);
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++NumOperands;
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} else {
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// TODO: this discards MAC/FMA instructions for now, let's add it later
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LLVM_DEBUG(dbgs() << " failed: no old operand in DPP instruction,"
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" TBD\n");
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Fail = true;
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break;
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}
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if (auto *Mod0 = TII->getNamedOperand(OrigMI,
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AMDGPU::OpName::src0_modifiers)) {
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assert(NumOperands == AMDGPU::getNamedOperandIdx(DPPOp,
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AMDGPU::OpName::src0_modifiers));
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assert(0LL == (Mod0->getImm() & ~(SISrcMods::ABS | SISrcMods::NEG)));
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DPPInst.addImm(Mod0->getImm());
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++NumOperands;
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} else if (AMDGPU::getNamedOperandIdx(DPPOp,
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AMDGPU::OpName::src0_modifiers) != -1) {
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DPPInst.addImm(0);
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++NumOperands;
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}
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auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0);
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assert(Src0);
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if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src0)) {
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LLVM_DEBUG(dbgs() << " failed: src0 is illegal\n");
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Fail = true;
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break;
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}
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DPPInst.add(*Src0);
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DPPInst->getOperand(NumOperands).setIsKill(false);
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++NumOperands;
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if (auto *Mod1 = TII->getNamedOperand(OrigMI,
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AMDGPU::OpName::src1_modifiers)) {
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assert(NumOperands == AMDGPU::getNamedOperandIdx(DPPOp,
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AMDGPU::OpName::src1_modifiers));
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assert(0LL == (Mod1->getImm() & ~(SISrcMods::ABS | SISrcMods::NEG)));
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DPPInst.addImm(Mod1->getImm());
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++NumOperands;
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} else if (AMDGPU::getNamedOperandIdx(DPPOp,
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AMDGPU::OpName::src1_modifiers) != -1) {
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DPPInst.addImm(0);
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++NumOperands;
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}
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if (auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1)) {
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if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src1)) {
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LLVM_DEBUG(dbgs() << " failed: src1 is illegal\n");
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Fail = true;
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break;
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}
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DPPInst.add(*Src1);
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++NumOperands;
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}
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if (auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2)) {
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if (!TII->getNamedOperand(*DPPInst.getInstr(), AMDGPU::OpName::src2) ||
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!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src2)) {
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LLVM_DEBUG(dbgs() << " failed: src2 is illegal\n");
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Fail = true;
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break;
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}
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DPPInst.add(*Src2);
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}
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DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl));
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DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask));
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DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask));
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DPPInst.addImm(CombBCZ ? 1 : 0);
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} while (false);
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if (Fail) {
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DPPInst.getInstr()->eraseFromParent();
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return nullptr;
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}
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LLVM_DEBUG(dbgs() << " combined: " << *DPPInst.getInstr());
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return DPPInst.getInstr();
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}
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static bool isIdentityValue(unsigned OrigMIOp, MachineOperand *OldOpnd) {
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assert(OldOpnd->isImm());
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switch (OrigMIOp) {
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default: break;
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case AMDGPU::V_ADD_U32_e32:
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case AMDGPU::V_ADD_U32_e64:
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case AMDGPU::V_ADD_CO_U32_e32:
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case AMDGPU::V_ADD_CO_U32_e64:
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case AMDGPU::V_OR_B32_e32:
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case AMDGPU::V_OR_B32_e64:
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case AMDGPU::V_SUBREV_U32_e32:
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case AMDGPU::V_SUBREV_U32_e64:
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case AMDGPU::V_SUBREV_CO_U32_e32:
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case AMDGPU::V_SUBREV_CO_U32_e64:
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case AMDGPU::V_MAX_U32_e32:
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case AMDGPU::V_MAX_U32_e64:
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case AMDGPU::V_XOR_B32_e32:
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case AMDGPU::V_XOR_B32_e64:
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if (OldOpnd->getImm() == 0)
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return true;
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break;
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case AMDGPU::V_AND_B32_e32:
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case AMDGPU::V_AND_B32_e64:
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case AMDGPU::V_MIN_U32_e32:
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case AMDGPU::V_MIN_U32_e64:
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if (static_cast<uint32_t>(OldOpnd->getImm()) ==
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std::numeric_limits<uint32_t>::max())
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return true;
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break;
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case AMDGPU::V_MIN_I32_e32:
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case AMDGPU::V_MIN_I32_e64:
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if (static_cast<int32_t>(OldOpnd->getImm()) ==
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std::numeric_limits<int32_t>::max())
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return true;
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break;
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case AMDGPU::V_MAX_I32_e32:
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case AMDGPU::V_MAX_I32_e64:
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if (static_cast<int32_t>(OldOpnd->getImm()) ==
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std::numeric_limits<int32_t>::min())
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return true;
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break;
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case AMDGPU::V_MUL_I32_I24_e32:
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case AMDGPU::V_MUL_I32_I24_e64:
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case AMDGPU::V_MUL_U32_U24_e32:
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case AMDGPU::V_MUL_U32_U24_e64:
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if (OldOpnd->getImm() == 1)
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return true;
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break;
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}
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return false;
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}
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MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI,
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MachineInstr &MovMI,
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RegSubRegPair CombOldVGPR,
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MachineOperand *OldOpndValue,
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bool CombBCZ) const {
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assert(CombOldVGPR.Reg);
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if (!CombBCZ && OldOpndValue && OldOpndValue->isImm()) {
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auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);
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if (!Src1 || !Src1->isReg()) {
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LLVM_DEBUG(dbgs() << " failed: no src1 or it isn't a register\n");
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return nullptr;
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}
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if (!isIdentityValue(OrigMI.getOpcode(), OldOpndValue)) {
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LLVM_DEBUG(dbgs() << " failed: old immediate isn't an identity\n");
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return nullptr;
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}
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CombOldVGPR = getRegSubRegPair(*Src1);
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if (!isOfRegClass(CombOldVGPR, AMDGPU::VGPR_32RegClass, *MRI)) {
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LLVM_DEBUG(dbgs() << " failed: src1 isn't a VGPR32 register\n");
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return nullptr;
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}
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}
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return createDPPInst(OrigMI, MovMI, CombOldVGPR, CombBCZ);
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}
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// returns true if MI doesn't have OpndName immediate operand or the
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// operand has Value
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bool GCNDPPCombine::hasNoImmOrEqual(MachineInstr &MI, unsigned OpndName,
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int64_t Value, int64_t Mask) const {
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auto *Imm = TII->getNamedOperand(MI, OpndName);
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if (!Imm)
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return true;
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|
|
assert(Imm->isImm());
|
||
|
|
return (Imm->getImm() & Mask) == Value;
|
||
|
|
}
|
||
|
|
|
||
|
|
bool GCNDPPCombine::combineDPPMov(MachineInstr &MovMI) const {
|
||
|
|
assert(MovMI.getOpcode() == AMDGPU::V_MOV_B32_dpp);
|
||
|
|
LLVM_DEBUG(dbgs() << "\nDPP combine: " << MovMI);
|
||
|
|
|
||
|
|
auto *DstOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst);
|
||
|
|
assert(DstOpnd && DstOpnd->isReg());
|
||
|
|
auto DPPMovReg = DstOpnd->getReg();
|
||
|
|
if (DPPMovReg.isPhysical()) {
|
||
|
|
LLVM_DEBUG(dbgs() << " failed: dpp move writes physreg\n");
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
if (execMayBeModifiedBeforeAnyUse(*MRI, DPPMovReg, MovMI)) {
|
||
|
|
LLVM_DEBUG(dbgs() << " failed: EXEC mask should remain the same"
|
||
|
|
" for all uses\n");
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
auto *RowMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask);
|
||
|
|
assert(RowMaskOpnd && RowMaskOpnd->isImm());
|
||
|
|
auto *BankMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask);
|
||
|
|
assert(BankMaskOpnd && BankMaskOpnd->isImm());
|
||
|
|
const bool MaskAllLanes = RowMaskOpnd->getImm() == 0xF &&
|
||
|
|
BankMaskOpnd->getImm() == 0xF;
|
||
|
|
|
||
|
|
auto *BCZOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bound_ctrl);
|
||
|
|
assert(BCZOpnd && BCZOpnd->isImm());
|
||
|
|
bool BoundCtrlZero = BCZOpnd->getImm();
|
||
|
|
|
||
|
|
auto *OldOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::old);
|
||
|
|
auto *SrcOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0);
|
||
|
|
assert(OldOpnd && OldOpnd->isReg());
|
||
|
|
assert(SrcOpnd && SrcOpnd->isReg());
|
||
|
|
if (OldOpnd->getReg().isPhysical() || SrcOpnd->getReg().isPhysical()) {
|
||
|
|
LLVM_DEBUG(dbgs() << " failed: dpp move reads physreg\n");
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
auto * const OldOpndValue = getOldOpndValue(*OldOpnd);
|
||
|
|
// OldOpndValue is either undef (IMPLICIT_DEF) or immediate or something else
|
||
|
|
// We could use: assert(!OldOpndValue || OldOpndValue->isImm())
|
||
|
|
// but the third option is used to distinguish undef from non-immediate
|
||
|
|
// to reuse IMPLICIT_DEF instruction later
|
||
|
|
assert(!OldOpndValue || OldOpndValue->isImm() || OldOpndValue == OldOpnd);
|
||
|
|
|
||
|
|
bool CombBCZ = false;
|
||
|
|
|
||
|
|
if (MaskAllLanes && BoundCtrlZero) { // [1]
|
||
|
|
CombBCZ = true;
|
||
|
|
} else {
|
||
|
|
if (!OldOpndValue || !OldOpndValue->isImm()) {
|
||
|
|
LLVM_DEBUG(dbgs() << " failed: the DPP mov isn't combinable\n");
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (OldOpndValue->getParent()->getParent() != MovMI.getParent()) {
|
||
|
|
LLVM_DEBUG(dbgs() <<
|
||
|
|
" failed: old reg def and mov should be in the same BB\n");
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (OldOpndValue->getImm() == 0) {
|
||
|
|
if (MaskAllLanes) {
|
||
|
|
assert(!BoundCtrlZero); // by check [1]
|
||
|
|
CombBCZ = true;
|
||
|
|
}
|
||
|
|
} else if (BoundCtrlZero) {
|
||
|
|
assert(!MaskAllLanes); // by check [1]
|
||
|
|
LLVM_DEBUG(dbgs() <<
|
||
|
|
" failed: old!=0 and bctrl:0 and not all lanes isn't combinable\n");
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
LLVM_DEBUG(dbgs() << " old=";
|
||
|
|
if (!OldOpndValue)
|
||
|
|
dbgs() << "undef";
|
||
|
|
else
|
||
|
|
dbgs() << *OldOpndValue;
|
||
|
|
dbgs() << ", bound_ctrl=" << CombBCZ << '\n');
|
||
|
|
|
||
|
|
SmallVector<MachineInstr*, 4> OrigMIs, DPPMIs;
|
||
|
|
DenseMap<MachineInstr*, SmallVector<unsigned, 4>> RegSeqWithOpNos;
|
||
|
|
auto CombOldVGPR = getRegSubRegPair(*OldOpnd);
|
||
|
|
// try to reuse previous old reg if its undefined (IMPLICIT_DEF)
|
||
|
|
if (CombBCZ && OldOpndValue) { // CombOldVGPR should be undef
|
||
|
|
CombOldVGPR = RegSubRegPair(
|
||
|
|
MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass));
|
||
|
|
auto UndefInst = BuildMI(*MovMI.getParent(), MovMI, MovMI.getDebugLoc(),
|
||
|
|
TII->get(AMDGPU::IMPLICIT_DEF), CombOldVGPR.Reg);
|
||
|
|
DPPMIs.push_back(UndefInst.getInstr());
|
||
|
|
}
|
||
|
|
|
||
|
|
OrigMIs.push_back(&MovMI);
|
||
|
|
bool Rollback = true;
|
||
|
|
SmallVector<MachineOperand*, 16> Uses;
|
||
|
|
|
||
|
|
for (auto &Use : MRI->use_nodbg_operands(DPPMovReg)) {
|
||
|
|
Uses.push_back(&Use);
|
||
|
|
}
|
||
|
|
|
||
|
|
while (!Uses.empty()) {
|
||
|
|
MachineOperand *Use = Uses.pop_back_val();
|
||
|
|
Rollback = true;
|
||
|
|
|
||
|
|
auto &OrigMI = *Use->getParent();
|
||
|
|
LLVM_DEBUG(dbgs() << " try: " << OrigMI);
|
||
|
|
|
||
|
|
auto OrigOp = OrigMI.getOpcode();
|
||
|
|
if (OrigOp == AMDGPU::REG_SEQUENCE) {
|
||
|
|
Register FwdReg = OrigMI.getOperand(0).getReg();
|
||
|
|
unsigned FwdSubReg = 0;
|
||
|
|
|
||
|
|
if (execMayBeModifiedBeforeAnyUse(*MRI, FwdReg, OrigMI)) {
|
||
|
|
LLVM_DEBUG(dbgs() << " failed: EXEC mask should remain the same"
|
||
|
|
" for all uses\n");
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
unsigned OpNo, E = OrigMI.getNumOperands();
|
||
|
|
for (OpNo = 1; OpNo < E; OpNo += 2) {
|
||
|
|
if (OrigMI.getOperand(OpNo).getReg() == DPPMovReg) {
|
||
|
|
FwdSubReg = OrigMI.getOperand(OpNo + 1).getImm();
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!FwdSubReg)
|
||
|
|
break;
|
||
|
|
|
||
|
|
for (auto &Op : MRI->use_nodbg_operands(FwdReg)) {
|
||
|
|
if (Op.getSubReg() == FwdSubReg)
|
||
|
|
Uses.push_back(&Op);
|
||
|
|
}
|
||
|
|
RegSeqWithOpNos[&OrigMI].push_back(OpNo);
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (TII->isVOP3(OrigOp)) {
|
||
|
|
if (!TII->hasVALU32BitEncoding(OrigOp)) {
|
||
|
|
LLVM_DEBUG(dbgs() << " failed: VOP3 hasn't e32 equivalent\n");
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
// check if other than abs|neg modifiers are set (opsel for example)
|
||
|
|
const int64_t Mask = ~(SISrcMods::ABS | SISrcMods::NEG);
|
||
|
|
if (!hasNoImmOrEqual(OrigMI, AMDGPU::OpName::src0_modifiers, 0, Mask) ||
|
||
|
|
!hasNoImmOrEqual(OrigMI, AMDGPU::OpName::src1_modifiers, 0, Mask) ||
|
||
|
|
!hasNoImmOrEqual(OrigMI, AMDGPU::OpName::clamp, 0) ||
|
||
|
|
!hasNoImmOrEqual(OrigMI, AMDGPU::OpName::omod, 0)) {
|
||
|
|
LLVM_DEBUG(dbgs() << " failed: VOP3 has non-default modifiers\n");
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
} else if (!TII->isVOP1(OrigOp) && !TII->isVOP2(OrigOp)) {
|
||
|
|
LLVM_DEBUG(dbgs() << " failed: not VOP1/2/3\n");
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
auto *Src0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0);
|
||
|
|
auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);
|
||
|
|
if (Use != Src0 && !(Use == Src1 && OrigMI.isCommutable())) { // [1]
|
||
|
|
LLVM_DEBUG(dbgs() << " failed: no suitable operands\n");
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
assert(Src0 && "Src1 without Src0?");
|
||
|
|
if (Src1 && Src1->isIdenticalTo(*Src0)) {
|
||
|
|
assert(Src1->isReg());
|
||
|
|
LLVM_DEBUG(
|
||
|
|
dbgs()
|
||
|
|
<< " " << OrigMI
|
||
|
|
<< " failed: DPP register is used more than once per instruction\n");
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
LLVM_DEBUG(dbgs() << " combining: " << OrigMI);
|
||
|
|
if (Use == Src0) {
|
||
|
|
if (auto *DPPInst = createDPPInst(OrigMI, MovMI, CombOldVGPR,
|
||
|
|
OldOpndValue, CombBCZ)) {
|
||
|
|
DPPMIs.push_back(DPPInst);
|
||
|
|
Rollback = false;
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
assert(Use == Src1 && OrigMI.isCommutable()); // by check [1]
|
||
|
|
auto *BB = OrigMI.getParent();
|
||
|
|
auto *NewMI = BB->getParent()->CloneMachineInstr(&OrigMI);
|
||
|
|
BB->insert(OrigMI, NewMI);
|
||
|
|
if (TII->commuteInstruction(*NewMI)) {
|
||
|
|
LLVM_DEBUG(dbgs() << " commuted: " << *NewMI);
|
||
|
|
if (auto *DPPInst = createDPPInst(*NewMI, MovMI, CombOldVGPR,
|
||
|
|
OldOpndValue, CombBCZ)) {
|
||
|
|
DPPMIs.push_back(DPPInst);
|
||
|
|
Rollback = false;
|
||
|
|
}
|
||
|
|
} else
|
||
|
|
LLVM_DEBUG(dbgs() << " failed: cannot be commuted\n");
|
||
|
|
NewMI->eraseFromParent();
|
||
|
|
}
|
||
|
|
if (Rollback)
|
||
|
|
break;
|
||
|
|
OrigMIs.push_back(&OrigMI);
|
||
|
|
}
|
||
|
|
|
||
|
|
Rollback |= !Uses.empty();
|
||
|
|
|
||
|
|
for (auto *MI : *(Rollback? &DPPMIs : &OrigMIs))
|
||
|
|
MI->eraseFromParent();
|
||
|
|
|
||
|
|
if (!Rollback) {
|
||
|
|
for (auto &S : RegSeqWithOpNos) {
|
||
|
|
if (MRI->use_nodbg_empty(S.first->getOperand(0).getReg())) {
|
||
|
|
S.first->eraseFromParent();
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
while (!S.second.empty())
|
||
|
|
S.first->getOperand(S.second.pop_back_val()).setIsUndef(true);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return !Rollback;
|
||
|
|
}
|
||
|
|
|
||
|
|
bool GCNDPPCombine::runOnMachineFunction(MachineFunction &MF) {
|
||
|
|
auto &ST = MF.getSubtarget<GCNSubtarget>();
|
||
|
|
if (!ST.hasDPP() || skipFunction(MF.getFunction()))
|
||
|
|
return false;
|
||
|
|
|
||
|
|
MRI = &MF.getRegInfo();
|
||
|
|
TII = ST.getInstrInfo();
|
||
|
|
|
||
|
|
bool Changed = false;
|
||
|
|
for (auto &MBB : MF) {
|
||
|
|
for (auto I = MBB.rbegin(), E = MBB.rend(); I != E;) {
|
||
|
|
auto &MI = *I++;
|
||
|
|
if (MI.getOpcode() == AMDGPU::V_MOV_B32_dpp && combineDPPMov(MI)) {
|
||
|
|
Changed = true;
|
||
|
|
++NumDPPMovsCombined;
|
||
|
|
} else if (MI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO) {
|
||
|
|
auto Split = TII->expandMovDPP64(MI);
|
||
|
|
for (auto M : { Split.first, Split.second }) {
|
||
|
|
if (combineDPPMov(*M))
|
||
|
|
++NumDPPMovsCombined;
|
||
|
|
}
|
||
|
|
Changed = true;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return Changed;
|
||
|
|
}
|