464 lines
17 KiB
TableGen
464 lines
17 KiB
TableGen
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//===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains DAG node definitions for the AMDGPU target.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// AMDGPU DAG Profiles
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//===----------------------------------------------------------------------===//
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def AMDGPUDTIntTernaryOp : SDTypeProfile<1, 3, [
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SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>
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]>;
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def AMDGPULdExpOp : SDTypeProfile<1, 2,
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[SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
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>;
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def AMDGPUFPClassOp : SDTypeProfile<1, 2,
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[SDTCisInt<0>, SDTCisFP<1>, SDTCisInt<2>]
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>;
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def AMDGPUFPPackOp : SDTypeProfile<1, 2,
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[SDTCisFP<1>, SDTCisSameAs<1, 2>]
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>;
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def AMDGPUIntPackOp : SDTypeProfile<1, 2,
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[SDTCisInt<1>, SDTCisSameAs<1, 2>]
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>;
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def AMDGPUDivScaleOp : SDTypeProfile<2, 3,
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[SDTCisFP<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisSameAs<0, 4>]
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>;
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// float, float, float, vcc
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def AMDGPUFmasOp : SDTypeProfile<1, 4,
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[SDTCisFP<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<4>]
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>;
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def AMDGPUKillSDT : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
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def AMDGPUIfOp : SDTypeProfile<1, 2,
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[SDTCisVT<0, i1>, SDTCisVT<1, i1>, SDTCisVT<2, OtherVT>]
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>;
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def AMDGPUElseOp : SDTypeProfile<1, 2,
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[SDTCisVT<0, i1>, SDTCisVT<1, i1>, SDTCisVT<2, OtherVT>]
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>;
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def AMDGPULoopOp : SDTypeProfile<0, 2,
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[SDTCisVT<0, i1>, SDTCisVT<1, OtherVT>]
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>;
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def AMDGPUIfBreakOp : SDTypeProfile<1, 2,
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[SDTCisVT<0, i1>, SDTCisVT<1, i1>, SDTCisVT<2, i1>]
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>;
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//===----------------------------------------------------------------------===//
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// AMDGPU DAG Nodes
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//
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def AMDGPUif : SDNode<"AMDGPUISD::IF", AMDGPUIfOp, [SDNPHasChain]>;
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def AMDGPUelse : SDNode<"AMDGPUISD::ELSE", AMDGPUElseOp, [SDNPHasChain]>;
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def AMDGPUloop : SDNode<"AMDGPUISD::LOOP", AMDGPULoopOp, [SDNPHasChain]>;
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def callseq_start : SDNode<"ISD::CALLSEQ_START",
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SDCallSeqStart<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>,
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[SDNPHasChain, SDNPOutGlue]
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>;
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def callseq_end : SDNode<"ISD::CALLSEQ_END",
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SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>,
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]
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>;
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def AMDGPUcall : SDNode<"AMDGPUISD::CALL",
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SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
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SDNPVariadic]
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>;
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def AMDGPUtc_return: SDNode<"AMDGPUISD::TC_RETURN",
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SDTypeProfile<0, 3, [SDTCisPtrTy<0>]>,
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[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]
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>;
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def AMDGPUtrap : SDNode<"AMDGPUISD::TRAP",
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SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>,
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[SDNPHasChain, SDNPVariadic, SDNPSideEffect, SDNPInGlue]
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>;
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def AMDGPUconstdata_ptr : SDNode<
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"AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 1, [SDTCisVT<0, iPTR>,
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SDTCisVT<0, iPTR>]>
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>;
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// This argument to this node is a dword address.
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def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>;
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// Force dependencies for vector trunc stores
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def R600dummy_chain : SDNode<"AMDGPUISD::DUMMY_CHAIN", SDTNone, [SDNPHasChain]>;
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def AMDGPUcos_impl : SDNode<"AMDGPUISD::COS_HW", SDTFPUnaryOp>;
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def AMDGPUsin_impl : SDNode<"AMDGPUISD::SIN_HW", SDTFPUnaryOp>;
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// out = a - floor(a)
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def AMDGPUfract_impl : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>;
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// out = 1.0 / a
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def AMDGPUrcp_impl : SDNode<"AMDGPUISD::RCP", SDTFPUnaryOp>;
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// out = 1.0 / sqrt(a)
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def AMDGPUrsq_impl : SDNode<"AMDGPUISD::RSQ", SDTFPUnaryOp>;
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def AMDGPUrcp_legacy_impl : SDNode<"AMDGPUISD::RCP_LEGACY", SDTFPUnaryOp>;
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def AMDGPUrcp_iflag : SDNode<"AMDGPUISD::RCP_IFLAG", SDTFPUnaryOp>;
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// out = 1.0 / sqrt(a) result clamped to +/- max_float.
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def AMDGPUrsq_clamp_impl : SDNode<"AMDGPUISD::RSQ_CLAMP", SDTFPUnaryOp>;
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def AMDGPUldexp_impl : SDNode<"AMDGPUISD::LDEXP", AMDGPULdExpOp>;
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def AMDGPUpkrtz_f16_f32_impl : SDNode<"AMDGPUISD::CVT_PKRTZ_F16_F32", AMDGPUFPPackOp>;
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def AMDGPUpknorm_i16_f32_impl : SDNode<"AMDGPUISD::CVT_PKNORM_I16_F32", AMDGPUFPPackOp>;
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def AMDGPUpknorm_u16_f32_impl : SDNode<"AMDGPUISD::CVT_PKNORM_U16_F32", AMDGPUFPPackOp>;
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def AMDGPUpk_i16_i32_impl : SDNode<"AMDGPUISD::CVT_PK_I16_I32", AMDGPUIntPackOp>;
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def AMDGPUpk_u16_u32_impl : SDNode<"AMDGPUISD::CVT_PK_U16_U32", AMDGPUIntPackOp>;
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def AMDGPUfp_to_f16 : SDNode<"AMDGPUISD::FP_TO_FP16" , SDTFPToIntOp>;
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def AMDGPUfp16_zext : SDNode<"AMDGPUISD::FP16_ZEXT" , SDTFPToIntOp>;
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def AMDGPUfp_class_impl : SDNode<"AMDGPUISD::FP_CLASS", AMDGPUFPClassOp>;
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// out = max(a, b) a and b are floats, where a nan comparison fails.
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// This is not commutative because this gives the second operand:
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// x < nan ? x : nan -> nan
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// nan < x ? nan : x -> x
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def AMDGPUfmax_legacy : SDNode<"AMDGPUISD::FMAX_LEGACY", SDTFPBinOp,
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[]
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>;
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def AMDGPUfmul_legacy_impl : SDNode<"AMDGPUISD::FMUL_LEGACY", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]
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>;
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// out = min(a, b) a and b are floats, where a nan comparison fails.
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def AMDGPUfmin_legacy : SDNode<"AMDGPUISD::FMIN_LEGACY", SDTFPBinOp,
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[]
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>;
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// FIXME: TableGen doesn't like commutative instructions with more
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// than 2 operands.
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// out = max(a, b, c) a, b and c are floats
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def AMDGPUfmax3 : SDNode<"AMDGPUISD::FMAX3", SDTFPTernaryOp,
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[/*SDNPCommutative, SDNPAssociative*/]
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>;
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// out = max(a, b, c) a, b, and c are signed ints
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def AMDGPUsmax3 : SDNode<"AMDGPUISD::SMAX3", AMDGPUDTIntTernaryOp,
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[/*SDNPCommutative, SDNPAssociative*/]
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>;
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// out = max(a, b, c) a, b and c are unsigned ints
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def AMDGPUumax3 : SDNode<"AMDGPUISD::UMAX3", AMDGPUDTIntTernaryOp,
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[/*SDNPCommutative, SDNPAssociative*/]
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>;
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// out = min(a, b, c) a, b and c are floats
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def AMDGPUfmin3 : SDNode<"AMDGPUISD::FMIN3", SDTFPTernaryOp,
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[/*SDNPCommutative, SDNPAssociative*/]
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>;
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// out = min(a, b, c) a, b and c are signed ints
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def AMDGPUsmin3 : SDNode<"AMDGPUISD::SMIN3", AMDGPUDTIntTernaryOp,
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[/*SDNPCommutative, SDNPAssociative*/]
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>;
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// out = min(a, b) a and b are unsigned ints
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def AMDGPUumin3 : SDNode<"AMDGPUISD::UMIN3", AMDGPUDTIntTernaryOp,
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[/*SDNPCommutative, SDNPAssociative*/]
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>;
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// out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
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def AMDGPUcarry : SDNode<"AMDGPUISD::CARRY", SDTIntBinOp, []>;
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// out = (src1 > src0) ? 1 : 0
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def AMDGPUborrow : SDNode<"AMDGPUISD::BORROW", SDTIntBinOp, []>;
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def AMDGPUSetCCOp : SDTypeProfile<1, 3, [ // setcc
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SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
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]>;
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def AMDGPUsetcc : SDNode<"AMDGPUISD::SETCC", AMDGPUSetCCOp>;
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def AMDGPUfma : SDNode<"AMDGPUISD::FMA_W_CHAIN", SDTFPTernaryOp, [
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SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
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def AMDGPUmul : SDNode<"AMDGPUISD::FMUL_W_CHAIN", SDTFPBinOp, [
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SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
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def AMDGPUcvt_f32_ubyte0 : SDNode<"AMDGPUISD::CVT_F32_UBYTE0",
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SDTIntToFPOp, []>;
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def AMDGPUcvt_f32_ubyte1 : SDNode<"AMDGPUISD::CVT_F32_UBYTE1",
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SDTIntToFPOp, []>;
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def AMDGPUcvt_f32_ubyte2 : SDNode<"AMDGPUISD::CVT_F32_UBYTE2",
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SDTIntToFPOp, []>;
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def AMDGPUcvt_f32_ubyte3 : SDNode<"AMDGPUISD::CVT_F32_UBYTE3",
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SDTIntToFPOp, []>;
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// urecip - This operation is a helper for integer division, it returns the
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// result of 1 / a as a fractional unsigned integer.
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// out = (2^32 / a) + e
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// e is rounding error
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def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>;
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// Special case divide preop and flags.
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def AMDGPUdiv_scale : SDNode<"AMDGPUISD::DIV_SCALE", AMDGPUDivScaleOp>;
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// Special case divide FMA with scale and flags (src0 = Quotient,
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// src1 = Denominator, src2 = Numerator).
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def AMDGPUdiv_fmas_impl : SDNode<"AMDGPUISD::DIV_FMAS", AMDGPUFmasOp,
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[SDNPOptInGlue]>;
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// Single or double precision division fixup.
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// Special case divide fixup and flags(src0 = Quotient, src1 =
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// Denominator, src2 = Numerator).
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def AMDGPUdiv_fixup_impl : SDNode<"AMDGPUISD::DIV_FIXUP", SDTFPTernaryOp>;
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def AMDGPUfmad_ftz_impl : SDNode<"AMDGPUISD::FMAD_FTZ", SDTFPTernaryOp>;
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def AMDGPUregister_load : SDNode<"AMDGPUISD::REGISTER_LOAD",
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SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
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[SDNPHasChain, SDNPMayLoad]>;
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def AMDGPUregister_store : SDNode<"AMDGPUISD::REGISTER_STORE",
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SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
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[SDNPHasChain, SDNPMayStore]>;
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// MSKOR instructions are atomic memory instructions used mainly for storing
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// 8-bit and 16-bit values. The definition is:
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//
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// MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src)
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//
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// src0: vec4(src, 0, 0, mask)
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// src1: dst - rat offset (aka pointer) in dwords
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def AMDGPUstore_mskor : SDNode<"AMDGPUISD::STORE_MSKOR",
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SDTypeProfile<0, 2, []>,
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[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
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def AMDGPUatomic_cmp_swap : SDNode<"AMDGPUISD::ATOMIC_CMP_SWAP",
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SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisVec<2>]>,
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[SDNPHasChain, SDNPMayStore, SDNPMayLoad,
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SDNPMemOperand]>;
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def AMDGPUround : SDNode<"ISD::FROUND",
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SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>>;
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def AMDGPUbfe_u32_impl : SDNode<"AMDGPUISD::BFE_U32", AMDGPUDTIntTernaryOp>;
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def AMDGPUbfe_i32_impl : SDNode<"AMDGPUISD::BFE_I32", AMDGPUDTIntTernaryOp>;
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def AMDGPUbfi : SDNode<"AMDGPUISD::BFI", AMDGPUDTIntTernaryOp>;
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def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
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def AMDGPUffbh_u32_impl : SDNode<"AMDGPUISD::FFBH_U32", SDTIntBitCountUnaryOp>;
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def AMDGPUffbh_i32_impl : SDNode<"AMDGPUISD::FFBH_I32", SDTIntBitCountUnaryOp>;
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def AMDGPUffbl_b32_impl : SDNode<"AMDGPUISD::FFBL_B32", SDTIntBitCountUnaryOp>;
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// Signed and unsigned 24-bit multiply. The highest 8-bits are ignore
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// when performing the multiply. The result is a 32-bit value.
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def AMDGPUmul_u24_impl : SDNode<"AMDGPUISD::MUL_U24", SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]
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>;
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def AMDGPUmul_i24_impl : SDNode<"AMDGPUISD::MUL_I24", SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]
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>;
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def AMDGPUmulhi_u24 : SDNode<"AMDGPUISD::MULHI_U24", SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]
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>;
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def AMDGPUmulhi_i24 : SDNode<"AMDGPUISD::MULHI_I24", SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]
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>;
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def AMDGPUmad_u24 : SDNode<"AMDGPUISD::MAD_U24", AMDGPUDTIntTernaryOp,
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[]
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>;
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def AMDGPUmad_i24 : SDNode<"AMDGPUISD::MAD_I24", AMDGPUDTIntTernaryOp,
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[]
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>;
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def AMDGPUsmed3 : SDNode<"AMDGPUISD::SMED3", AMDGPUDTIntTernaryOp,
|
||
|
|
[]
|
||
|
|
>;
|
||
|
|
|
||
|
|
def AMDGPUumed3 : SDNode<"AMDGPUISD::UMED3", AMDGPUDTIntTernaryOp,
|
||
|
|
[]
|
||
|
|
>;
|
||
|
|
|
||
|
|
def AMDGPUfmed3_impl : SDNode<"AMDGPUISD::FMED3", SDTFPTernaryOp, []>;
|
||
|
|
|
||
|
|
def AMDGPUfdot2_impl : SDNode<"AMDGPUISD::FDOT2",
|
||
|
|
SDTypeProfile<1, 4, [SDTCisSameAs<0, 3>, SDTCisSameAs<1, 2>,
|
||
|
|
SDTCisFP<0>, SDTCisVec<1>,
|
||
|
|
SDTCisInt<4>]>,
|
||
|
|
[]>;
|
||
|
|
|
||
|
|
def AMDGPUperm : SDNode<"AMDGPUISD::PERM", AMDGPUDTIntTernaryOp, []>;
|
||
|
|
|
||
|
|
// SI+ export
|
||
|
|
def AMDGPUExportOp : SDTypeProfile<0, 8, [
|
||
|
|
SDTCisInt<0>, // i8 tgt
|
||
|
|
SDTCisInt<1>, // i8 en
|
||
|
|
// i32 or f32 src0
|
||
|
|
SDTCisSameAs<3, 2>, // f32 src1
|
||
|
|
SDTCisSameAs<4, 2>, // f32 src2
|
||
|
|
SDTCisSameAs<5, 2>, // f32 src3
|
||
|
|
SDTCisInt<6>, // i1 compr
|
||
|
|
// skip done
|
||
|
|
SDTCisInt<1> // i1 vm
|
||
|
|
|
||
|
|
]>;
|
||
|
|
|
||
|
|
|
||
|
|
def R600ExportOp : SDTypeProfile<0, 7, [SDTCisFP<0>, SDTCisInt<1>]>;
|
||
|
|
|
||
|
|
def R600_EXPORT: SDNode<"AMDGPUISD::R600_EXPORT", R600ExportOp,
|
||
|
|
[SDNPHasChain, SDNPSideEffect]>;
|
||
|
|
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
// Flow Control Profile Types
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
// Branch instruction where second and third are basic blocks
|
||
|
|
def SDTIL_BRCond : SDTypeProfile<0, 2, [
|
||
|
|
SDTCisVT<0, OtherVT>
|
||
|
|
]>;
|
||
|
|
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
// Flow Control DAG Nodes
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
def IL_brcond : SDNode<"AMDGPUISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>;
|
||
|
|
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
// Call/Return DAG Nodes
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
def AMDGPUendpgm : SDNode<"AMDGPUISD::ENDPGM", SDTNone,
|
||
|
|
[SDNPHasChain, SDNPOptInGlue]>;
|
||
|
|
|
||
|
|
def AMDGPUreturn_to_epilog : SDNode<"AMDGPUISD::RETURN_TO_EPILOG", SDTNone,
|
||
|
|
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
|
||
|
|
|
||
|
|
def AMDGPUret_flag : SDNode<"AMDGPUISD::RET_FLAG", SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
|
||
|
|
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]
|
||
|
|
>;
|
||
|
|
|
||
|
|
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
// Intrinsic/Custom node compatibility PatFrags
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
|
||
|
|
def AMDGPUrcp : PatFrags<(ops node:$src), [(int_amdgcn_rcp node:$src),
|
||
|
|
(AMDGPUrcp_impl node:$src)]>;
|
||
|
|
def AMDGPUrcp_legacy : PatFrags<(ops node:$src), [(int_amdgcn_rcp_legacy node:$src),
|
||
|
|
(AMDGPUrcp_legacy_impl node:$src)]>;
|
||
|
|
|
||
|
|
def AMDGPUrsq : PatFrags<(ops node:$src), [(int_amdgcn_rsq node:$src),
|
||
|
|
(AMDGPUrsq_impl node:$src)]>;
|
||
|
|
|
||
|
|
def AMDGPUrsq_clamp : PatFrags<(ops node:$src), [(int_amdgcn_rsq_clamp node:$src),
|
||
|
|
(AMDGPUrsq_clamp_impl node:$src)]>;
|
||
|
|
|
||
|
|
def AMDGPUsin : PatFrags<(ops node:$src), [(int_amdgcn_sin node:$src),
|
||
|
|
(AMDGPUsin_impl node:$src)]>;
|
||
|
|
def AMDGPUcos : PatFrags<(ops node:$src), [(int_amdgcn_cos node:$src),
|
||
|
|
(AMDGPUcos_impl node:$src)]>;
|
||
|
|
def AMDGPUfract : PatFrags<(ops node:$src), [(int_amdgcn_fract node:$src),
|
||
|
|
(AMDGPUfract_impl node:$src)]>;
|
||
|
|
|
||
|
|
def AMDGPUldexp : PatFrags<(ops node:$src0, node:$src1),
|
||
|
|
[(int_amdgcn_ldexp node:$src0, node:$src1),
|
||
|
|
(AMDGPUldexp_impl node:$src0, node:$src1)]>;
|
||
|
|
|
||
|
|
def AMDGPUfp_class : PatFrags<(ops node:$src0, node:$src1),
|
||
|
|
[(int_amdgcn_class node:$src0, node:$src1),
|
||
|
|
(AMDGPUfp_class_impl node:$src0, node:$src1)]>;
|
||
|
|
|
||
|
|
def AMDGPUfmed3 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
|
||
|
|
[(int_amdgcn_fmed3 node:$src0, node:$src1, node:$src2),
|
||
|
|
(AMDGPUfmed3_impl node:$src0, node:$src1, node:$src2)]>;
|
||
|
|
|
||
|
|
def AMDGPUdiv_fixup : PatFrags<(ops node:$src0, node:$src1, node:$src2),
|
||
|
|
[(int_amdgcn_div_fixup node:$src0, node:$src1, node:$src2),
|
||
|
|
(AMDGPUdiv_fixup_impl node:$src0, node:$src1, node:$src2)]>;
|
||
|
|
|
||
|
|
def AMDGPUffbh_i32 : PatFrags<(ops node:$src),
|
||
|
|
[(int_amdgcn_sffbh node:$src),
|
||
|
|
(AMDGPUffbh_i32_impl node:$src)]>;
|
||
|
|
|
||
|
|
def AMDGPUffbh_u32 : PatFrags<(ops node:$src),
|
||
|
|
[(ctlz_zero_undef node:$src),
|
||
|
|
(AMDGPUffbh_u32_impl node:$src)]>;
|
||
|
|
|
||
|
|
def AMDGPUffbl_b32 : PatFrags<(ops node:$src),
|
||
|
|
[(cttz_zero_undef node:$src),
|
||
|
|
(AMDGPUffbl_b32_impl node:$src)]>;
|
||
|
|
|
||
|
|
def AMDGPUpkrtz_f16_f32 : PatFrags<(ops node:$src0, node:$src1),
|
||
|
|
[(int_amdgcn_cvt_pkrtz node:$src0, node:$src1),
|
||
|
|
(AMDGPUpkrtz_f16_f32_impl node:$src0, node:$src1)]>;
|
||
|
|
|
||
|
|
def AMDGPUpknorm_i16_f32 : PatFrags<(ops node:$src0, node:$src1),
|
||
|
|
[(int_amdgcn_cvt_pknorm_i16 node:$src0, node:$src1),
|
||
|
|
(AMDGPUpknorm_i16_f32_impl node:$src0, node:$src1)]>;
|
||
|
|
|
||
|
|
def AMDGPUpknorm_u16_f32 : PatFrags<(ops node:$src0, node:$src1),
|
||
|
|
[(int_amdgcn_cvt_pknorm_u16 node:$src0, node:$src1),
|
||
|
|
(AMDGPUpknorm_u16_f32_impl node:$src0, node:$src1)]>;
|
||
|
|
|
||
|
|
def AMDGPUpk_i16_i32 : PatFrags<(ops node:$src0, node:$src1),
|
||
|
|
[(int_amdgcn_cvt_pk_i16 node:$src0, node:$src1),
|
||
|
|
(AMDGPUpk_i16_i32_impl node:$src0, node:$src1)]>;
|
||
|
|
|
||
|
|
def AMDGPUpk_u16_u32 : PatFrags<(ops node:$src0, node:$src1),
|
||
|
|
[(int_amdgcn_cvt_pk_u16 node:$src0, node:$src1),
|
||
|
|
(AMDGPUpk_u16_u32_impl node:$src0, node:$src1)]>;
|
||
|
|
|
||
|
|
def AMDGPUfmad_ftz : PatFrags<(ops node:$src0, node:$src1, node:$src2),
|
||
|
|
[(int_amdgcn_fmad_ftz node:$src0, node:$src1, node:$src2),
|
||
|
|
(AMDGPUfmad_ftz_impl node:$src0, node:$src1, node:$src2)]>;
|
||
|
|
|
||
|
|
def AMDGPUmul_u24 : PatFrags<(ops node:$src0, node:$src1),
|
||
|
|
[(int_amdgcn_mul_u24 node:$src0, node:$src1),
|
||
|
|
(AMDGPUmul_u24_impl node:$src0, node:$src1)]>;
|
||
|
|
|
||
|
|
def AMDGPUmul_i24 : PatFrags<(ops node:$src0, node:$src1),
|
||
|
|
[(int_amdgcn_mul_i24 node:$src0, node:$src1),
|
||
|
|
(AMDGPUmul_i24_impl node:$src0, node:$src1)]>;
|
||
|
|
|
||
|
|
def AMDGPUbfe_i32 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
|
||
|
|
[(int_amdgcn_sbfe node:$src0, node:$src1, node:$src2),
|
||
|
|
(AMDGPUbfe_i32_impl node:$src0, node:$src1, node:$src2)]>;
|
||
|
|
|
||
|
|
def AMDGPUbfe_u32 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
|
||
|
|
[(int_amdgcn_ubfe node:$src0, node:$src1, node:$src2),
|
||
|
|
(AMDGPUbfe_u32_impl node:$src0, node:$src1, node:$src2)]>;
|
||
|
|
|
||
|
|
def AMDGPUfmul_legacy : PatFrags<(ops node:$src0, node:$src1),
|
||
|
|
[(int_amdgcn_fmul_legacy node:$src0, node:$src1),
|
||
|
|
(AMDGPUfmul_legacy_impl node:$src0, node:$src1)]>;
|
||
|
|
|
||
|
|
def AMDGPUfdot2 : PatFrags<(ops node:$src0, node:$src1, node:$src2, node:$clamp),
|
||
|
|
[(int_amdgcn_fdot2 node:$src0, node:$src1, node:$src2, node:$clamp),
|
||
|
|
(AMDGPUfdot2_impl node:$src0, node:$src1, node:$src2, node:$clamp)]>;
|
||
|
|
|
||
|
|
def AMDGPUdiv_fmas : PatFrags<(ops node:$src0, node:$src1, node:$src2, node:$vcc),
|
||
|
|
[(int_amdgcn_div_fmas node:$src0, node:$src1, node:$src2, node:$vcc),
|
||
|
|
(AMDGPUdiv_fmas_impl node:$src0, node:$src1, node:$src2, node:$vcc)]>;
|